index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
synth
Commit message (
Expand
)
Author
Age
Files
Lines
*
synth-vhdl_stmts: check subtype compatibility for scalar signal assoc.
Tristan Gingold
2022-04-15
3
-1
/
+93
*
synth: do not emit a warning for the gclk attribute. Fix #2035
Tristan Gingold
2022-04-13
1
-1
/
+2
*
synth: handle type declarations in vunit. Fix #2034
Tristan Gingold
2022-04-13
2
-12
/
+18
*
synth: add support for subtype declaration in vunits. Fix #2033
Tristan Gingold
2022-04-13
2
-3
/
+8
*
elab-vhdl_insts: also recurse for instantiations in vunits.
Tristan Gingold
2022-04-08
1
-74
/
+93
*
synth-vhdl_stmts: emit an error message on missing return. Fix #2019
Tristan Gingold
2022-04-06
1
-1
/
+3
*
synth-vhdl_insts: also finalize entity declarations
Tristan Gingold
2022-04-06
1
-0
/
+1
*
synth: do not add info for element subtype (except for arrays).
Tristan Gingold
2022-04-05
3
-17
/
+33
*
synth: handle individual assoc of unbounded interface. Fix #2023
Tristan Gingold
2022-04-04
2
-1
/
+4
*
synth: handle shared variable without default value.
Tristan Gingold
2022-04-04
2
-1
/
+4
*
grt: extract grt-vhdl_types from grt-types
Tristan Gingold
2022-03-22
1
-0
/
+1
*
synth-vhdl_expr: minor refactoring - add comments
Tristan Gingold
2022-03-20
1
-16
/
+34
*
synth-vhdl_expr(value2logvec): fix vlen handling. Fix #2013
Tristan Gingold
2022-03-20
1
-7
/
+13
*
synth-vhdl_context: adjust mask. Fix #2011
Tristan Gingold
2022-03-18
1
-1
/
+1
*
netlists-disp_verilog: fix disp_const_bit
Tristan Gingold
2022-03-12
1
-2
/
+2
*
synth: check matching bounds for concatenation
Tristan Gingold
2022-03-11
2
-2
/
+4
*
synth: add debug_bt
Tristan Gingold
2022-03-08
4
-0
/
+56
*
synth: handle concatenation of unbounded types. Fix #1993
Tristan Gingold
2022-03-08
9
-111
/
+64
*
synth-vhdl_oper: implement <= for arrays. Fix #1991
Tristan Gingold
2022-03-02
2
-7
/
+19
*
elab-vhdl_expr.adb(exec_name_subtype): handle indexed names. Fix #1986
Tristan Gingold
2022-03-02
1
-0
/
+8
*
synth: fix handling of record constraints in subtype. Fix #1961
Tristan Gingold
2022-02-22
1
-1
/
+9
*
elab-vhdl_values.adb: fix a typo. Fix #1968
Tristan Gingold
2022-02-18
1
-2
/
+2
*
synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977
Tristan Gingold
2022-02-17
1
-27
/
+30
*
synth: properly propagate bound errors. Fix #1972
Tristan Gingold
2022-02-17
4
-16
/
+38
*
synth-vhdl_oper: handle bit condition operator. Fix #1971
Tristan Gingold
2022-02-16
1
-1
/
+2
*
synth-vhdl_aggr: fix mismatch. Fix #1962
Tristan Gingold
2022-02-05
1
-1
/
+6
*
synth: fix handling of std_logic_unsigned."-" for negative numbers.
Tristan Gingold
2022-01-18
1
-8
/
+12
*
synth: adjust handling of subprogram calls in package instantiation. Fix #1947
Tristan Gingold
2022-01-16
1
-3
/
+14
*
synth: do not annotate generic types in package. Fix #1949
Tristan Gingold
2022-01-15
1
-11
/
+19
*
synth: handle macro-expanded package body. Fix #1948
Tristan Gingold
2022-01-14
2
-2
/
+4
*
synth: handle alias of alias. Fix #1945
Tristan Gingold
2022-01-12
1
-2
/
+15
*
synth: refine handling of interface type. Fix #1944
Tristan Gingold
2022-01-10
1
-2
/
+6
*
synth: ignore use clauses in finalization Fix #1942
Tristan Gingold
2022-01-05
1
-0
/
+2
*
synth: handle package instantiation in declarations. Fix #1938
Tristan Gingold
2022-01-03
4
-1
/
+12
*
synth: add assertions
Tristan Gingold
2021-12-19
1
-0
/
+4
*
ghdldrv: fix crash due to double initialization
Tristan Gingold
2021-12-19
1
-2
/
+0
*
synth: handle interface type in generics. For #412
Tristan Gingold
2021-12-15
3
-25
/
+41
*
Fix opening files relative to the current vhdl
Matt Johnston
2021-12-07
1
-0
/
+2
*
synth: add --latches option to enable latches. Fix #938
Tristan Gingold
2021-12-06
2
-1
/
+8
*
synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926
Tristan Gingold
2021-11-29
1
-19
/
+11
*
synth memories: also accept constant signal as memory initial value
Tristan Gingold
2021-11-28
2
-4
/
+9
*
elab-vhdl_objtypes.adb: add an assertion
Tristan Gingold
2021-11-28
1
-0
/
+2
*
elab-vhdl_insts.adb: do not try to elaborate foreign instances twice
Tristan Gingold
2021-11-28
1
-1
/
+6
*
synth-vhdl_insts.adb: split synth_Instantiate_Module
Tristan Gingold
2021-11-28
1
-14
/
+26
*
synth: add hooks to support elaboration of foreign instances
Tristan Gingold
2021-11-28
10
-32
/
+108
*
synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920
Tristan Gingold
2021-11-21
1
-0
/
+7
*
synth: put direction into port desc
Tristan Gingold
2021-11-17
8
-31
/
+30
*
synth: use a global table for instances attributes
Tristan Gingold
2021-11-17
6
-168
/
+117
*
synth: renaming to instance_attributes.
Tristan Gingold
2021-11-17
11
-66
/
+72
*
synth/netlists-disp_verilog: display port attributes
Tristan Gingold
2021-11-17
1
-18
/
+42
[next]