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| author | Tristan Gingold <tgingold@free.fr> | 2021-12-15 08:18:10 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-12-15 08:18:10 +0100 |
| commit | 9df3cb21ad765f38561fff0a568ce94359d4d977 (patch) | |
| tree | 162232a463e986d01e65fc476c40093596b84e09 /src/synth | |
| parent | c661e58db492f14b22e2ab59e58a8abde6e74c10 (diff) | |
| download | ghdl-9df3cb21ad765f38561fff0a568ce94359d4d977.tar.gz ghdl-9df3cb21ad765f38561fff0a568ce94359d4d977.tar.bz2 ghdl-9df3cb21ad765f38561fff0a568ce94359d4d977.zip | |
synth: handle interface type in generics. For #412
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 12 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_types.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 50 |
3 files changed, 41 insertions, 25 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index 71adc953d..b8b53517d 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -106,6 +106,15 @@ package body Elab.Vhdl_Insts is Create_Package_Interface (Sub_Inst, Inter, Pkg_Inst); end; + when Iir_Kind_Interface_Type_Declaration => + declare + Act_Typ : Type_Acc; + begin + Act_Typ := Synth_Subtype_Indication + (Syn_Inst, Get_Actual (Assoc)); + Create_Subtype_Object (Sub_Inst, Get_Type (Inter), Act_Typ); + end; + when Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_File_Declaration | Iir_Kind_Interface_Signal_Declaration @@ -113,8 +122,7 @@ package body Elab.Vhdl_Insts is | Iir_Kind_Interface_Terminal_Declaration => raise Internal_Error; - when Iir_Kinds_Interface_Subprogram_Declaration - | Iir_Kind_Interface_Type_Declaration => + when Iir_Kinds_Interface_Subprogram_Declaration => raise Internal_Error; end case; diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 300f57427..7d726d154 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -530,7 +530,9 @@ package body Elab.Vhdl_Types is when Iir_Kinds_Denoting_Name => Atype := Get_Named_Entity (Atype); when Iir_Kind_Subtype_Declaration - | Iir_Kind_Type_Declaration => + | Iir_Kind_Type_Declaration + | Iir_Kind_Subtype_Attribute + | Iir_Kind_Interface_Type_Declaration => -- Type already declared, so already handled. return Null_Node; when Iir_Kind_Array_Subtype_Definition diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index dfb42b532..235d9ed8e 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -254,28 +254,34 @@ package body Synth.Vhdl_Insts is Gen_Decl := Generics; while Gen_Decl /= Null_Node loop - Gen := Get_Value (Params.Syn_Inst, Gen_Decl); - Strip_Const (Gen); - case Gen.Typ.Kind is - when Type_Discrete => - declare - S : constant String := - Uns64'Image (To_Uns64 (Read_Discrete (Gen))); - begin - if Len + S'Length > Str_Len then - Has_Hash := True; - Hash_Const (Ctxt, Gen.Val, Gen.Typ); - else - Str (Len + 1 .. Len + S'Length) := S; - pragma Assert (Str (Len + 1) = ' '); - Str (Len + 1) := '_'; -- Overwrite the space. - Len := Len + S'Length; - end if; - end; - when others => - Has_Hash := True; - Hash_Const (Ctxt, Gen.Val, Gen.Typ); - end case; + if Get_Kind (Gen_Decl) = Iir_Kind_Interface_Constant_Declaration + then + Gen := Get_Value (Params.Syn_Inst, Gen_Decl); + Strip_Const (Gen); + case Gen.Typ.Kind is + when Type_Discrete => + declare + S : constant String := + Uns64'Image (To_Uns64 (Read_Discrete (Gen))); + begin + if Len + S'Length > Str_Len then + Has_Hash := True; + Hash_Const (Ctxt, Gen.Val, Gen.Typ); + else + Str (Len + 1 .. Len + S'Length) := S; + pragma Assert (Str (Len + 1) = ' '); + Str (Len + 1) := '_'; -- Overwrite the space. + Len := Len + S'Length; + end if; + end; + when others => + Has_Hash := True; + Hash_Const (Ctxt, Gen.Val, Gen.Typ); + end case; + else + -- TODO: add a unique number (index) + null; + end if; Gen_Decl := Get_Chain (Gen_Decl); end loop; |