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* synth: fix handling of record constraints in subtype. Fix #1961Tristan Gingold2022-02-221-1/+9
* elab-vhdl_values.adb: fix a typo. Fix #1968Tristan Gingold2022-02-181-2/+2
* synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977Tristan Gingold2022-02-171-27/+30
* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-174-16/+38
* synth-vhdl_oper: handle bit condition operator. Fix #1971Tristan Gingold2022-02-161-1/+2
* synth-vhdl_aggr: fix mismatch. Fix #1962Tristan Gingold2022-02-051-1/+6
* synth: fix handling of std_logic_unsigned."-" for negative numbers.Tristan Gingold2022-01-181-8/+12
* synth: adjust handling of subprogram calls in package instantiation. Fix #1947Tristan Gingold2022-01-161-3/+14
* synth: do not annotate generic types in package. Fix #1949Tristan Gingold2022-01-151-11/+19
* synth: handle macro-expanded package body. Fix #1948Tristan Gingold2022-01-142-2/+4
* synth: handle alias of alias. Fix #1945Tristan Gingold2022-01-121-2/+15
* synth: refine handling of interface type. Fix #1944Tristan Gingold2022-01-101-2/+6
* synth: ignore use clauses in finalization Fix #1942Tristan Gingold2022-01-051-0/+2
* synth: handle package instantiation in declarations. Fix #1938Tristan Gingold2022-01-034-1/+12
* synth: add assertionsTristan Gingold2021-12-191-0/+4
* ghdldrv: fix crash due to double initializationTristan Gingold2021-12-191-2/+0
* synth: handle interface type in generics. For #412Tristan Gingold2021-12-153-25/+41
* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-062-1/+8
* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
* Add commentsTristan Gingold2021-11-171-0/+2
* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
* synth: also handle rol. For #1909Tristan Gingold2021-11-111-0/+5
* synth: handle ror from numeric_std. Fix #1909Tristan Gingold2021-11-111-1/+4
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-093-9/+14
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-052-25/+28
* synth: Support alias declarations in vunittmeissner2021-11-023-5/+14
* synth: do full elaboration before synthesisTristan Gingold2021-11-0158-1996/+5291
* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
* synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896Tristan Gingold2021-10-181-1/+5
* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-2/+4
* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
* synth-vhdl_decls.adb: also detect unassigned variables.Tristan Gingold2021-10-091-11/+4
* netlists-disp_verilog: fix name for memory initializationTristan Gingold2021-09-281-3/+4
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