iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: introduce iir_kind_association_element_by_name	Tristan Gingold	2021-08-06	1	-3/+4
\|
*	synth: minor renaming in netlists-memories	Tristan Gingold	2021-06-30	3	-10/+11
\|
*	synth-vhdl_context.adb(Is_Full): consider fractional words.	Tristan Gingold	2021-06-23	1	-2/+16
\|
*	synth-vhdl_stmts: add location on Addidx	Tristan Gingold	2021-06-21	1	-0/+2
\|
*	synth-environment: early transformation of dyn_insert to dyn_insert_en	Tristan Gingold	2021-06-21	4	-25/+59
\| \| \| \|	Simplifies memory extraction
*	synth-vhdl_stmts: merge static extract before dyn_extract.	Tristan Gingold	2021-06-21	1	-4/+2
\| \| \| \|	No reasons to use an extra gate.
*	synth-vhdl_expr: adjust width of memidx for indexed names.	Tristan Gingold	2021-06-21	1	-1/+1
\| \| \| \|	In general the width of memidx is ignored, but it's better to correctly set it
*	synth: add a gate on an optimization to simplify memory handling.	Tristan Gingold	2021-06-17	2	-67/+38
\|
*	netlists-memories: strengthen dyn_extract mux reduction. Fix #1781	Tristan Gingold	2021-06-16	2	-1/+52
\|
*	synth: minor fixes	Tristan Gingold	2021-06-15	2	-9/+8
\|
*	netlists-memories: avoid a crash on uninitialized ROM.	Tristan Gingold	2021-05-24	1	-1/+9
\|
*	netlists-disp_verilog: fix display of constants	Tristan Gingold	2021-05-07	1	-10/+20
\|
*	synth-environment: add Set/Get_Kind, Wire_Unset	Tristan Gingold	2021-05-07	2	-1/+26
\|
*	netlists-cleanup: do not remove self-assigned output gate	Tristan Gingold	2021-05-07	1	-23/+30
\|
*	netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.	Tristan Gingold	2021-05-04	1	-74/+14
\|
*	synth: add verilog output	Tristan Gingold	2021-04-28	2	-0/+1417
\|
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	14	-45/+49
\|
*	synth: use a generic version of synth-environment.	Tristan Gingold	2021-04-27	18	-363/+479
\|
*	synth-insts.adb: avoid a crash after an error during instantiation. Fix #1734	Tristan Gingold	2021-04-23	2	-1/+9
\|
*	synth-vhdl_oper.adb: handle resize uns/uns. For #1731	Tristan Gingold	2021-04-21	1	-0/+12
\|
*	synth-vhdl_oper.adb: adjust previous patch and test	Tristan Gingold	2021-04-21	1	-1/+12
\| \| \| \| \|	resize with two signed parameters extract the size of the second parameter to resize the first one.
*	synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731	Tristan Gingold	2021-04-21	1	-0/+1
\| \| \| \|	With an hint from T.Meissner
*	synth: extract synth-memtype from synth-objtypes	Tristan Gingold	2021-04-21	15	-124/+193
\|
*	synth: renaming (synth-heap -> synth-vhdl_heap)	Tristan Gingold	2021-04-16	5	-11/+11
\|
*	synth: renaming (synth-static_proc -> synth-vhdl_static_proc)	Tristan Gingold	2021-04-16	3	-6/+6
\|
*	synth: refactoring (synth.files_operations -> synth.vhdl_files)	Tristan Gingold	2021-04-16	6	-11/+11
\|
*	synth: renaming (synth.oper -> synth.vhdl_oper)	Tristan Gingold	2021-04-16	4	-11/+11
\|
*	synth: refactoring (synth.aggr -> synth.vhdl_aggr)	Tristan Gingold	2021-04-16	3	-7/+7
\|
*	synth: rename synth-context to synth-vhdl_context	Tristan Gingold	2021-04-16	15	-23/+23
\|
*	synth: avoid crash in case of non-elaboratable generic.	Tristan Gingold	2021-04-15	2	-4/+10
\|
*	vhdl and libraries: add support for binding to a foreign module	Tristan Gingold	2021-04-05	1	-0/+5
\|
*	netlists-disp_vhdl: do not display edge net when not needed. Fix #1703	Tristan Gingold	2021-03-29	3	-25/+49
\|
*	synth: expand ports for record. Fix #1675	Tristan Gingold	2021-03-27	3	-65/+270
\|
*	netlists-dump: also dump attributes	Tristan Gingold	2021-03-17	3	-74/+168
\|
*	synth: handle loc attribute (for ports). Fix #1682	Tristan Gingold	2021-03-17	2	-1/+5
\|
*	netlists: do not remove net gates that have an attribute	Tristan Gingold	2021-03-17	3	-25/+36
\|
*	synth-expr.adb: add comments	Tristan Gingold	2021-03-14	1	-0/+5
\|
*	synth-expr.adb: handle const right in synth_short_circuit. Fix #1685	Tristan Gingold	2021-03-14	1	-0/+6
\|
*	synth-oper: handle const for numeric_std.match Fix #1679	Tristan Gingold	2021-03-13	1	-0/+1
\|
*	synth-expr: allow non-simple name for FF clocks. Fix #1681	Tristan Gingold	2021-03-13	1	-12/+17
\|
*	synth: handle attributes of length 0. Fix #1680	Tristan Gingold	2021-03-13	2	-3/+6
\|
*	Include directory structure proposal.	Michał Kruszewski	2021-03-07	2	-1/+1
\|
*	synth: handle pow and arctan from ieee.math_real. Fix #1665	Tristan Gingold	2021-02-27	1	-0/+16
\|
*	synth-stmts: handle attributes in block and generate statements. Fix #1658	Tristan Gingold	2021-02-21	1	-0/+5
\|
*	synth-expr: compute signess for range array attributes. Fix #1645	Tristan Gingold	2021-02-12	3	-17/+9
\|
*	netlists-folds: add comments	Tristan Gingold	2021-02-09	1	-0/+4
\|
*	Add support for PSL onehot/onehot0 functions (#1633)	T. Meissner	2021-02-09	1	-0/+92
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: parse PSL onehot/onehot0 builtin calls. For #662 * update pyGHDL bindings * Synthesis of PSL built-in onehot/onehot0 function. * testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662 * doc: add info about PSL built-in functions onehot()/onehot0() for #662 * synth: refactor synthesis of onehot/onehot0 functions Co-authored-by: eine <eine@users.noreply.github.com>
*	update license headers	umarcor	2021-02-05	90	-461/+282
\|
*	synth: handle to_stdlogicvector. For #1628	Tristan Gingold	2021-02-04	1	-1/+2
\|
*	std_names: add gclk. For #1610	Tristan Gingold	2021-01-25	2	-0/+9
\| \| \| \|	Regenerate python files.