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* elab-vhdl_insts: set global variable with top instanceTristan Gingold2023-04-182-0/+5
* synth: preliminary support of flat netlistsTristan Gingold2023-04-172-71/+211
* netlists-memories: improve detection of inverted enableTristan Gingold2023-04-171-14/+30
* netlists-memories: factorize codeTristan Gingold2023-04-171-74/+27
* is_tribuf_net: refineTristan Gingold2023-04-161-3/+10
* netlists-memories: add commentsTristan Gingold2023-04-161-1/+5
* netlists-gates: add commentsTristan Gingold2023-04-161-0/+4
* synth: handle conditional variable assignment with no default.Tristan Gingold2023-04-141-2/+16
* synth: handle conv_signed. Fix #2408Tristan Gingold2023-04-142-2/+9
* synth: add checks for array conversionTristan Gingold2023-03-272-5/+42
* synth: adjust for iir_kind_package_instantiation_bodyTristan Gingold2023-03-274-8/+30
* synth-vhdl_insts: use the right synth instance for actual type.Tristan Gingold2023-03-261-2/+3
* synth_conditiona_signal_assignment: handle simple case directly.Tristan Gingold2023-03-141-46/+79
* synth: support selected signal assignmentTristan Gingold2023-03-091-0/+2
* synth-vhdl_oper: handle to_01. Fix #2372Tristan Gingold2023-03-051-0/+1
* synth-vhdl_stmts: handle unaffected in conditional variable assignmentsTristan Gingold2023-03-021-3/+11
* synth-vhd_oper: handle rising_edge for bit. For #2369Tristan Gingold2023-03-021-8/+11
* synth: handle unaffected in simple sequential signal assignment.Tristan Gingold2023-02-251-4/+9
* synth-vhdl_expr: improve subtype conversionTristan Gingold2023-02-221-69/+160
* synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vectorTristan Gingold2023-02-093-0/+43
* synth: preliminary work for PSL endpointsTristan Gingold2023-02-081-0/+17
* simul: improve support of PSL endpointsTristan Gingold2023-02-081-2/+11
* simul: improve handling of individual signal associationsTristan Gingold2023-02-081-3/+3
* synth: do not handle null-vectors for to_hstring.Tristan Gingold2023-02-082-1/+18
* synth: use same layout for records in memory as translateTristan Gingold2023-02-088-68/+227
* synth: preliminary work to compute access bounds sizeTristan Gingold2023-02-053-2/+128
* elab-vhdl_objtypes: rename acc_bnd_sz to acc_type_szTristan Gingold2023-02-053-7/+7
* elab-vhdl_debug: handle package in subprogramsTristan Gingold2023-02-041-0/+13
* translate: rework translate_object_subtype_indication.Tristan Gingold2023-02-021-5/+5
* elab-debugger: also pass top instance on break_timeTristan Gingold2023-01-312-3/+3
* synth: avoid a crash after errors in declarations. Fix #2334Tristan Gingold2023-01-301-18/+28
* synth: also fix crash for #2333Tristan Gingold2023-01-301-2/+4
* simul: use same packing order for nets and for values.Tristan Gingold2023-01-304-13/+47
* elab-debugger: improve current context for print commandTristan Gingold2023-01-303-6/+17
* elab-vhdl_debug: avoid a crash for lhTristan Gingold2023-01-301-0/+3
* netlists-rename: add commentsTristan Gingold2023-01-301-0/+2
* synth: represent access types as pointers in memoryTristan Gingold2023-01-2913-60/+125
* synth: simplify New_Sname_Artificial (prefix is not used)Tristan Gingold2023-01-294-78/+72
* elab-vhdl_annotations: refactoringTristan Gingold2023-01-291-35/+9
* vhdl: add Is_Owned_Subtype_IndicationTristan Gingold2023-01-291-21/+10
* synth: avoid a crash on subtype indication. Fix #2330Tristan Gingold2023-01-291-1/+1
* synth: handle bit reduction operators. Fix #2328Tristan Gingold2023-01-291-7/+14
* synth: improve support of interface typeTristan Gingold2023-01-282-30/+82
* elab-vhdl_annotations: remove useless codeTristan Gingold2023-01-281-18/+0
* synth-vhdl_eval: minor reformattingTristan Gingold2023-01-281-18/+18
* synth: fix incorrect check in array subtype indicationsTristan Gingold2023-01-281-2/+8
* synth-vhdl_oper: add bit-vect and vect-bit operations.Tristan Gingold2023-01-271-12/+24
* elab-memtype: add Read_Ptr, Write_PtrTristan Gingold2023-01-272-0/+22
* grt-files_operations: use grt.filesTristan Gingold2023-01-272-4/+5
* synth: add a check for bounds compatibilityTristan Gingold2023-01-251-4/+39
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