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| author | Tristan Gingold <tgingold@free.fr> | 2023-03-27 19:12:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-03-27 19:12:02 +0200 |
| commit | 5f105b010f4a2530ff52b9f62e4dc619e1225d01 (patch) | |
| tree | f299d928db81e189204245265467670780778572 /src/synth | |
| parent | 413db2f74665682693f899045feb4f5bdc108c03 (diff) | |
| download | ghdl-5f105b010f4a2530ff52b9f62e4dc619e1225d01.tar.gz ghdl-5f105b010f4a2530ff52b9f62e4dc619e1225d01.tar.bz2 ghdl-5f105b010f4a2530ff52b9f62e4dc619e1225d01.zip | |
synth: add checks for array conversion
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_types.ads | 5 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 42 |
2 files changed, 42 insertions, 5 deletions
diff --git a/src/synth/elab-vhdl_types.ads b/src/synth/elab-vhdl_types.ads index 4a7baffb3..625bb2eb5 100644 --- a/src/synth/elab-vhdl_types.ads +++ b/src/synth/elab-vhdl_types.ads @@ -45,6 +45,11 @@ package Elab.Vhdl_Types is function Synth_Bounds_From_Range (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Bound_Type; + procedure Check_Bound_Compatibility (Syn_Inst : Synth_Instance_Acc; + Loc : Node; + Bnd : Bound_Type; + Typ : Type_Acc); + function Create_Bounds_From_Length (Bounds : Discrete_Range_Type; Len : Iir_Index32) return Bound_Type; diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index e5ffd933f..b5093cb02 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -1699,11 +1699,43 @@ package body Synth.Vhdl_Expr is return No_Valtyp; end if; when Type_Vector - | Type_Unbounded_Vector => - return Val; - when Type_Array - | Type_Unbounded_Array => - return Val; + | Type_Array => + -- Check length, replace bounds. + declare + Src_Typ, Dst_Typ : Type_Acc; + begin + Src_Typ := Val.Typ; + Dst_Typ := Conv_Typ; + loop + if Src_Typ.Abound.Len /= Dst_Typ.Abound.Len then + Error_Msg_Synth (Syn_Inst, Loc, "array length mismatch"); + return No_Valtyp; + end if; + exit when Src_Typ.Alast; + Src_Typ := Src_Typ.Arr_El; + Dst_Typ := Dst_Typ.Arr_El; + end loop; + + return (Typ => Conv_Typ, Val => Val.Val); + end; + when Type_Unbounded_Vector + | Type_Unbounded_Array => + -- Check bounds fit in target + declare + Src_Typ, Dst_Typ : Type_Acc; + begin + Src_Typ := Val.Typ; + Dst_Typ := Conv_Typ; + loop + Elab.Vhdl_Types.Check_Bound_Compatibility + (Syn_Inst, Loc, Src_Typ.Abound, Dst_Typ.Uarr_Idx); + exit when Src_Typ.Alast; + Src_Typ := Src_Typ.Arr_El; + Dst_Typ := Dst_Typ.Arr_El; + end loop; + + return Val; + end; when Type_Bit | Type_Logic => return Val; |