iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: add hooks to support elaboration of foreign instances	Tristan Gingold	2021-11-28	1	-0/+3
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*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-5/+5
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*	synth: factorize code to create base instance	Tristan Gingold	2021-08-28	1	-0/+7
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*	synthesis.adb: abstract instance_passes	Tristan Gingold	2021-08-28	1	-0/+4
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*	synth: rename synth-context to synth-vhdl_context	Tristan Gingold	2021-04-16	1	-1/+1
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*	update license headers	umarcor	2021-02-05	1	-5/+3
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*	synth: top entity name is not anymore hashed by default.	Tristan Gingold	2020-03-01	1	-2/+7
\| \| \| \|	Use --top-name=hash to get the previous behaviour.
*	synth: refactoring to reduce global variables.	Tristan Gingold	2019-09-19	1	-2/+0
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*	synth-disp_vhdl: handle record for input ports.	Tristan Gingold	2019-09-03	1	-1/+3
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*	synth: handle instantiation (WIP)	Tristan Gingold	2019-07-10	1	-0/+2
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*	vhdl: rename iirs to vhdl.nodes	Tristan Gingold	2019-05-05	1	-1/+1
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*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+28