synth: do full elaboration before synthesis

1 files changed, 5 insertions, 5 deletions

diff --git a/src/synth/synthesis.ads b/src/synth/synthesis.ads
index 59688832e..30523c21d 100644
--- a/src/synth/synthesis.ads
+++ b/src/synth/synthesis.ads
@@ -22,15 +22,15 @@ with Vhdl.Nodes; use Vhdl.Nodes;
 with Netlists; use Netlists;
 with Netlists.Builders; use Netlists.Builders;
 
+with Elab.Vhdl_Context; use Elab.Vhdl_Context;
+
 with Synth.Context; use Synth.Context;
-with Synth.Vhdl_Context; use Synth.Vhdl_Context;
 with Synth.Flags; use Synth.Flags;
 
 package Synthesis is
-   procedure Synth_Design (Design : Iir;
-                           Encoding : Name_Encoding;
-                           M : out Module;
-                           Inst : out Synth_Instance_Acc);
+   function Synth_Design (Design : Iir;
+                          Inst : Synth_Instance_Acc;
+                          Encoding : Name_Encoding) return Module;
 
    --  Run cleanup/memory extraction/expand passes on M.
    procedure Instance_Passes (Ctxt : Context_Acc; M : Module);