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author | Tristan Gingold <tgingold@free.fr> | 2021-11-01 19:50:19 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-01 21:11:10 +0100 |
commit | 86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b (patch) | |
tree | e34bdcf719bdc08cb22a65e04ad67b57b0c06879 /src/synth/synthesis.ads | |
parent | 74043fa1aa40c375c7f299e6b5f1b6ea9150580e (diff) | |
download | ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.tar.gz ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.tar.bz2 ghdl-86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b.zip |
synth: do full elaboration before synthesis
Diffstat (limited to 'src/synth/synthesis.ads')
-rw-r--r-- | src/synth/synthesis.ads | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/synth/synthesis.ads b/src/synth/synthesis.ads index 59688832e..30523c21d 100644 --- a/src/synth/synthesis.ads +++ b/src/synth/synthesis.ads @@ -22,15 +22,15 @@ with Vhdl.Nodes; use Vhdl.Nodes; with Netlists; use Netlists; with Netlists.Builders; use Netlists.Builders; +with Elab.Vhdl_Context; use Elab.Vhdl_Context; + with Synth.Context; use Synth.Context; -with Synth.Vhdl_Context; use Synth.Vhdl_Context; with Synth.Flags; use Synth.Flags; package Synthesis is - procedure Synth_Design (Design : Iir; - Encoding : Name_Encoding; - M : out Module; - Inst : out Synth_Instance_Acc); + function Synth_Design (Design : Iir; + Inst : Synth_Instance_Acc; + Encoding : Name_Encoding) return Module; -- Run cleanup/memory extraction/expand passes on M. procedure Instance_Passes (Ctxt : Context_Acc; M : Module); |