diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-09-02 20:39:56 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-03 06:38:59 +0200 |
| commit | f8eab0dd6bffcb1a035b6a600bebe94991ab9629 (patch) | |
| tree | b7a258afeda8454abc735579ad900111169e1af9 /src/synth/synthesis.ads | |
| parent | dac322e43b97e0d3bfd9cdf0e98f1a7c458501cb (diff) | |
| download | ghdl-f8eab0dd6bffcb1a035b6a600bebe94991ab9629.tar.gz ghdl-f8eab0dd6bffcb1a035b6a600bebe94991ab9629.tar.bz2 ghdl-f8eab0dd6bffcb1a035b6a600bebe94991ab9629.zip | |
synth-disp_vhdl: handle record for input ports.
Diffstat (limited to 'src/synth/synthesis.ads')
| -rw-r--r-- | src/synth/synthesis.ads | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synthesis.ads b/src/synth/synthesis.ads index 703d190e0..ac458ff88 100644 --- a/src/synth/synthesis.ads +++ b/src/synth/synthesis.ads @@ -20,9 +20,11 @@ with Vhdl.Nodes; use Vhdl.Nodes; with Netlists; use Netlists; +with Synth.Context; use Synth.Context; package Synthesis is - function Synth_Design (Design : Iir) return Module; + procedure Synth_Design + (Design : Iir; M : out Module; Inst : out Synth_Instance_Acc); Global_Module : Module; |