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* synth: refactoring to reduce global variables.Tristan Gingold2019-09-191-2/+0
* synth-disp_vhdl: handle record for input ports.Tristan Gingold2019-09-031-1/+3
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-0/+2
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+28