iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl/psl: handle PSL inherit spec. For #1899	Tristan Gingold	2021-11-05	1	-15/+17
*	synth: Support alias declarations in vunit	tmeissner	2021-11-02	1	-2/+7
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-146/+85
*	synth: reject wait statement. Fix #1903	Tristan Gingold	2021-10-29	1	-0/+3
*	synth: Support PSL declarations in inline PSL	tmeissner	2021-10-14	1	-1/+2
*	synth: add support for sequence instance in vunit. Fix #1889	Tristan Gingold	2021-10-13	1	-2/+4
*	vhdl-canon: recurse for default block configuration of a vunit.	Tristan Gingold	2021-09-12	1	-7/+2
*	synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.	Tristan Gingold	2021-09-11	1	-2/+5
*	vhdl: allow constants in vunit declarations. Fix #1856	Tristan Gingold	2021-09-08	1	-0/+2
*	synth-vhdl_stmts.adb: do not expect configuration for vunit.	Tristan Gingold	2021-09-01	1	-3/+3
*	synth: handle PSL async_abort and sync_abort. For #1654	Tristan Gingold	2021-08-31	1	-1/+33
*	synth-vhdl_stmts: fix a crash on never triggered PSL assertion.	Tristan Gingold	2021-08-29	1	-0/+6
*	synth: improve result of is_positive	Tristan Gingold	2021-08-29	1	-1/+4
*	synth: do not remove signals with a keep attribute.	Tristan Gingold	2021-08-27	1	-1/+2
*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	1	-2/+0
*	synth-vhdl_stmts: add location on Addidx	Tristan Gingold	2021-06-21	1	-0/+2
*	synth-vhdl_stmts: merge static extract before dyn_extract.	Tristan Gingold	2021-06-21	1	-4/+2
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-0/+3856