iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth-vhdl_oper: handle more bit_vector operations. Fix #2074	Tristan Gingold	2022-06-05	1	-8/+13
*	synth-vhdl_oper: add hooks for bit edge	Tristan Gingold	2022-05-30	1	-0/+12
*	vhdl-nodes: move maximum/minimum out of predefined operator range	Tristan Gingold	2022-05-30	1	-18/+21
*	synth-vhdl_oper: add hook for falling edge, handle aliases.	Tristan Gingold	2022-05-29	1	-0/+4
*	synth-vhdl_oper: add an hook for rising_edge	Tristan Gingold	2022-05-23	1	-0/+4
*	synth: use same elements for unbounded arrays and vectors	Tristan Gingold	2022-05-22	1	-3/+3
*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-16/+16
*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-4/+4
*	synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062	Tristan Gingold	2022-05-17	1	-0/+1
*	synth: renaming (synth-static_oper -> synth-vhdl_eval)	Tristan Gingold	2022-04-27	1	-4/+4
*	synth: abstract code for reuse by evaluation	Tristan Gingold	2022-04-26	1	-1/+1
*	synth-static_oper: fully remove dependency on synth_instance	Tristan Gingold	2022-04-26	1	-8/+35
*	synth-static_oper: do not depend on instance for static operations.	Tristan Gingold	2022-04-26	1	-29/+5
*	synth: handle concatenation of unbounded types. Fix #1993	Tristan Gingold	2022-03-08	1	-8/+25
*	synth-vhdl_oper: implement <= for arrays. Fix #1991	Tristan Gingold	2022-03-02	1	-7/+17
*	synth-vhdl_oper: handle to_unsigned with an unsigned for size. Fix #1977	Tristan Gingold	2022-02-17	1	-27/+30
*	synth-vhdl_oper: handle bit condition operator. Fix #1971	Tristan Gingold	2022-02-16	1	-1/+2
*	synth: fix handling of std_logic_unsigned."-" for negative numbers.	Tristan Gingold	2022-01-18	1	-8/+12
*	synth: also handle rol. For #1909	Tristan Gingold	2021-11-11	1	-0/+5
*	synth: handle ror from numeric_std. Fix #1909	Tristan Gingold	2021-11-11	1	-1/+4
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-1/+4
*	synth-vhdl_oper: handle nor for boolean	Tristan Gingold	2021-09-14	1	-0/+1
*	synth: add build2_concat2 and use it for vhdl concat.	Tristan Gingold	2021-08-28	1	-4/+4
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-2/+2
*	synth-vhdl_oper.adb: handle resize uns/uns. For #1731	Tristan Gingold	2021-04-21	1	-0/+12
*	synth-vhdl_oper.adb: adjust previous patch and test	Tristan Gingold	2021-04-21	1	-1/+12
*	synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731	Tristan Gingold	2021-04-21	1	-0/+1
*	synth: extract synth-memtype from synth-objtypes	Tristan Gingold	2021-04-21	1	-0/+1
*	synth: renaming (synth.oper -> synth.vhdl_oper)	Tristan Gingold	2021-04-16	1	-0/+2151