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path: root/src/synth/synth-vhdl_expr.adb
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* elab: Rename Get/Set_Info to Get/Set_AnnTristan Gingold2023-01-201-1/+1
* simul: handle PSL endpointsTristan Gingold2023-01-181-0/+8
* synth: more refactoringTristan Gingold2023-01-141-2/+1
* synth: improve error propagation on slicesTristan Gingold2023-01-141-4/+14
* synth: report values in bound errorsTristan Gingold2023-01-121-8/+23
* synth: use same wording for direction mismatch as simulationTristan Gingold2023-01-121-1/+2
* synth: handle entity attributesTristan Gingold2023-01-111-2/+18
* synth: handle element attributeTristan Gingold2023-01-111-1/+5
* synth: check float ranges in subtype conversionTristan Gingold2023-01-111-2/+14
* synth: handle indexes in arrays conversionTristan Gingold2023-01-101-5/+63
* synth: fix handle of array attributesTristan Gingold2023-01-091-7/+6
* synth: handle subtype attribute in type prefixes.Tristan Gingold2023-01-091-0/+21
* synth: use same error message for null access as simulationTristan Gingold2023-01-061-1/+1
* synth: detect null access dereference, fix offset.Tristan Gingold2023-01-041-1/+7
* synth: introduce type_array_unboundedTristan Gingold2023-01-031-0/+3
* synth: fix handling of record subtypes for objectsTristan Gingold2023-01-031-0/+1
* synth: handle string literals in debugTristan Gingold2022-12-311-1/+2
* synth: check bounds for pos and val attributesTristan Gingold2022-12-261-3/+10
* simul: handle driving and driving_value attributesTristan Gingold2022-12-261-0/+13
* synth: handle instance_name attributeTristan Gingold2022-12-261-3/+9
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-0/+1
* synth: handle record conversionTristan Gingold2022-10-141-0/+3
* synth-vhdl_expr: support alias in indexed namesTristan Gingold2022-10-141-1/+2
* simul: handle last_event and last_activeTristan Gingold2022-10-131-0/+14
* synth: fix crashes on scalar attribute with anonymous subtype.Tristan Gingold2022-10-101-2/+2
* synth: avoid crash on invalid hdl in psl. Fix #2204Tristan Gingold2022-10-031-13/+34
* synth: avoid a crash on literal overflowTristan Gingold2022-10-011-1/+10
* synth: handle float-float conversionsTristan Gingold2022-09-301-3/+14
* simul: handle quiet attributeTristan Gingold2022-09-291-3/+15
* synth: handle guard signal in debuggerTristan Gingold2022-09-281-0/+1
* simul: handle last_value attributeTristan Gingold2022-09-281-0/+7
* synth: handle guard signal in expressionsTristan Gingold2022-09-281-0/+1
* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-251-30/+26
* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-251-48/+52
* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-191-1/+2
* simul: handle type conversions in port associationsTristan Gingold2022-09-181-38/+36
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-1/+2
* simul: handle active attributeTristan Gingold2022-09-161-1/+7
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
* synth: improve handling of complex typesTristan Gingold2022-09-151-2/+3
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-1/+2
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-1/+1
* synth: use areapoolsTristan Gingold2022-09-021-7/+15
* synth: handle type left/right attributesTristan Gingold2022-08-251-0/+14
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-16/+6
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-191-3/+0
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
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