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| author | Tristan Gingold <tgingold@free.fr> | 2022-12-25 20:25:28 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-12-26 10:25:20 +0100 |
| commit | 8a6be3328e812256abd7b01e965ac60630a70888 (patch) | |
| tree | 027b0ccd357f337c3d0bab6dbf027367f9d78b5e /src/synth/synth-vhdl_expr.adb | |
| parent | de6ca601a8e016b17b161d1e0fb4e0528381a977 (diff) | |
| download | ghdl-8a6be3328e812256abd7b01e965ac60630a70888.tar.gz ghdl-8a6be3328e812256abd7b01e965ac60630a70888.tar.bz2 ghdl-8a6be3328e812256abd7b01e965ac60630a70888.zip | |
synth: add value_sig_val to handle individual signal associations
Diffstat (limited to 'src/synth/synth-vhdl_expr.adb')
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 036e5a27e..83aecb420 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -2060,6 +2060,7 @@ package body Synth.Vhdl_Expr is Res := Synth_Name (Syn_Inst, Expr); if Res.Val /= null then if (Res.Val.Kind = Value_Signal + or else Res.Val.Kind = Value_Sig_Val or else (Res.Val.Kind = Value_Alias and then Res.Val.A_Obj.Kind = Value_Signal)) then |