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author | Tristan Gingold <tgingold@free.fr> | 2022-09-19 07:34:55 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-09-19 07:34:55 +0200 |
commit | a5f7e9e324210b5d73924e903f24e870572bb096 (patch) | |
tree | 1d82d34bf4f07b07b31bd72c3e7565df5b5735e0 /src/synth/synth-vhdl_expr.adb | |
parent | 8d3dcfb5bf4feffd59eaf2802b824059b3d75070 (diff) | |
download | ghdl-a5f7e9e324210b5d73924e903f24e870572bb096.tar.gz ghdl-a5f7e9e324210b5d73924e903f24e870572bb096.tar.bz2 ghdl-a5f7e9e324210b5d73924e903f24e870572bb096.zip |
synth: rename vhdl.annotations to elab.vhdl_annotations
Diffstat (limited to 'src/synth/synth-vhdl_expr.adb')
-rw-r--r-- | src/synth/synth-vhdl_expr.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 5698b7987..26f1f2ef5 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -27,7 +27,6 @@ with Vhdl.Std_Package; with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Evaluation; use Vhdl.Evaluation; -with Vhdl.Annotations; use Vhdl.Annotations; with PSL.Nodes; with PSL.Errors; @@ -38,6 +37,7 @@ with Netlists.Utils; use Netlists.Utils; with Netlists.Locations; with Elab.Memtype; use Elab.Memtype; +with Elab.Vhdl_Annotations; with Elab.Vhdl_Heap; use Elab.Vhdl_Heap; with Elab.Vhdl_Types; use Elab.Vhdl_Types; with Elab.Vhdl_Expr; @@ -474,6 +474,7 @@ package body Synth.Vhdl_Expr is Atype : Node; Dim : Dim_Type) return Bound_Type is + use Elab.Vhdl_Annotations; Info : constant Sim_Info_Acc := Get_Info (Atype); begin if Info = null then |