iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: add statement in context, adjust path/instance name attributes	Tristan Gingold	2022-12-31	1	-1/+1
*	synth: add value_sig_val to handle individual signal associations	Tristan Gingold	2022-12-26	1	-1/+2
*	synth: infere a dff (instead of an idff) when the init value is X	Tristan Gingold	2022-11-03	1	-5/+18
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-5/+8
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-2/+5
*	synth-vhdl_context: fix handling of alias in get_net. Fix #2177	Tristan Gingold	2022-08-14	1	-4/+3
*	synth/elab-vhdl_values: add Value_Terminal	Tristan Gingold	2022-07-25	1	-1/+2
*	elab-vhdl_values: add Create_Value_Quantity	Tristan Gingold	2022-07-16	1	-0/+2
*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	1	-1/+18
*	synth-vhdl_context: resize table before access. Fix #2049	Tristan Gingold	2022-05-02	1	-6/+14
*	synth-vhdl_context: adjust mask. Fix #2011	Tristan Gingold	2022-03-18	1	-1/+1
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-291/+172
*	synth: factorize code to create base instance	Tristan Gingold	2021-08-28	1	-13/+2
*	synth-vhdl_context.adb(Is_Full): consider fractional words.	Tristan Gingold	2021-06-23	1	-2/+16
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-1/+1
*	synth: use a generic version of synth-environment.	Tristan Gingold	2021-04-27	1	-1/+1
*	synth: rename synth-context to synth-vhdl_context	Tristan Gingold	2021-04-16	1	-0/+562