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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-10 09:47:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-10 18:45:58 +0200 |
| commit | ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c (patch) | |
| tree | 5e6184d1e4c3220a2d2f006027c0f9cf5b4af45f /src/synth/synth-vhdl_context.adb | |
| parent | 3d50ceb1772ec529ed168579d3d0b5603df96493 (diff) | |
| download | ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.tar.gz ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.tar.bz2 ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.zip | |
synth: fix and add checks for memory management.
Diffstat (limited to 'src/synth/synth-vhdl_context.adb')
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 7b6c81cbb..5326c4356 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -180,7 +180,7 @@ package body Synth.Vhdl_Context is else Wid := Alloc_Wire (Kind, (Obj, Otyp)); end if; - Val := Create_Value_Wire (Wid, Otyp); + Val := Create_Value_Wire (Wid, Otyp, Current_Pool); Create_Object (Syn_Inst, Obj, Val); end Create_Wire_Object; @@ -354,18 +354,21 @@ package body Synth.Vhdl_Context is Val.N := To_Uns32 (W); end Set_Value_Wire; - function Create_Value_Wire (W : Wire_Id) return Value_Acc + function Create_Value_Wire (W : Wire_Id; Pool : Areapool_Acc) + return Value_Acc is function To_Uns32 is new Ada.Unchecked_Conversion (Wire_Id, Uns32); begin - return Create_Value_Wire (To_Uns32 (W)); + return Create_Value_Wire (To_Uns32 (W), Pool); end Create_Value_Wire; - function Create_Value_Wire (W : Wire_Id; Wtype : Type_Acc) return Valtyp + function Create_Value_Wire (W : Wire_Id; + Wtype : Type_Acc; + Pool : Areapool_Acc) return Valtyp is pragma Assert (Wtype /= null); begin - return (Wtype, Create_Value_Wire (W)); + return (Wtype, Create_Value_Wire (W, Pool)); end Create_Value_Wire; function Create_Value_Net (N : Net) return Value_Acc |