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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-25 05:16:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-25 05:16:09 +0200 |
| commit | 54cf60d44d1110b127f6a81ee789eef4740630a1 (patch) | |
| tree | fe159529cf9dfb1bbb1e06b619e89fc76cc6c6d8 /src/synth/synth-vhdl_context.adb | |
| parent | 4fb0f50bc59eac444acb171040964dc73d3d105f (diff) | |
| download | ghdl-54cf60d44d1110b127f6a81ee789eef4740630a1.tar.gz ghdl-54cf60d44d1110b127f6a81ee789eef4740630a1.tar.bz2 ghdl-54cf60d44d1110b127f6a81ee789eef4740630a1.zip | |
synth/elab-vhdl_values: add Value_Terminal
Diffstat (limited to 'src/synth/synth-vhdl_context.adb')
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 6e498afdf..90e618e1e 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -448,7 +448,8 @@ package body Synth.Vhdl_Context is | Value_Signal | Value_Dyn_Alias => return False; - when Value_Quantity => + when Value_Quantity + | Value_Terminal => return False; when Value_Wire => declare |