iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth-vhdl-eval: handle more operations	Tristan Gingold	2022-06-05	1	-6/+6
*	synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_x	Tristan Gingold	2022-06-05	1	-1/+5
*	synth-vhdl_eval: handle more operators (nand, nor, xnor)	Tristan Gingold	2022-06-04	1	-0/+39
*	synth-vhdl_eval: handle vector match, numeric_bit.to_unsigned	Tristan Gingold	2022-05-31	1	-0/+13
*	synth-vhdl_eval: handle more operations (to_string, match)	Tristan Gingold	2022-05-31	1	-0/+65
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-1/+1
*	synth: extract synth-memtype from synth-objtypes	Tristan Gingold	2021-04-21	1	-1/+2
*	update license headers	umarcor	2021-02-05	1	-5/+3
*	synth: handle static to_bit and to_bitvector. Fix #1540	Tristan Gingold	2020-12-20	1	-0/+9
*	synth-static_oper: handle to_stdulogic. For #1534	Tristan Gingold	2020-12-13	1	-0/+4
*	synth-ieee-std-logic_1164: remove unused std_logic_vector declaration.	Tristan Gingold	2020-05-17	1	-4/+0
*	synth: use memtyp for synth-ieee-numeric_std, add more signed mul.	Tristan Gingold	2020-05-16	1	-0/+6
*	synth-static_oper: handle mul nat uns. Fix #1179	Tristan Gingold	2020-04-01	1	-0/+1
*	synth-static_oper: handle unsigned "<".	Tristan Gingold	2020-03-13	1	-0/+6
*	synth: handle static mul sgn sgn.	Tristan Gingold	2019-11-16	1	-1/+6
*	synth: handle static mul uns uns. Fix bit order for add.	Tristan Gingold	2019-11-16	1	-0/+12
*	synth: add support for static vector/vector or.	Tristan Gingold	2019-11-13	1	-1/+14
*	synth: handle static unsigned/unsigned add.	Tristan Gingold	2019-11-13	1	-0/+3
*	synth: introduce synth-static_oper.	Tristan Gingold	2019-11-13	1	-0/+54