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* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-111-0/+3
* synth: fix matching comparaison tablesTristan Gingold2023-01-111-27/+27
* synth-vhdl-eval: handle more operationsTristan Gingold2022-06-051-6/+6
* synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_xTristan Gingold2022-06-051-1/+5
* synth-vhdl_eval: handle more operators (nand, nor, xnor)Tristan Gingold2022-06-041-0/+39
* synth-vhdl_eval: handle vector match, numeric_bit.to_unsignedTristan Gingold2022-05-311-0/+13
* synth-vhdl_eval: handle more operations (to_string, match)Tristan Gingold2022-05-311-0/+65
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-1/+1
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-211-1/+2
* update license headersumarcor2021-02-051-5/+3
* synth: handle static to_bit and to_bitvector. Fix #1540Tristan Gingold2020-12-201-0/+9
* synth-static_oper: handle to_stdulogic. For #1534Tristan Gingold2020-12-131-0/+4
* synth-ieee-std-logic_1164: remove unused std_logic_vector declaration.Tristan Gingold2020-05-171-4/+0
* synth: use memtyp for synth-ieee-numeric_std, add more signed mul.Tristan Gingold2020-05-161-0/+6
* synth-static_oper: handle mul nat uns. Fix #1179Tristan Gingold2020-04-011-0/+1
* synth-static_oper: handle unsigned "<".Tristan Gingold2020-03-131-0/+6
* synth: handle static mul sgn sgn.Tristan Gingold2019-11-161-1/+6
* synth: handle static mul uns uns. Fix bit order for add.Tristan Gingold2019-11-161-0/+12
* synth: add support for static vector/vector or.Tristan Gingold2019-11-131-1/+14
* synth: handle static unsigned/unsigned add.Tristan Gingold2019-11-131-0/+3
* synth: introduce synth-static_oper.Tristan Gingold2019-11-131-0/+54