iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-22/+30
*	simul: add support for protected objects	Tristan Gingold	2022-09-08	1	-0/+23
*	elab-vhdl_values: factorize code	Tristan Gingold	2022-09-07	1	-18/+7
*	synth-vhdl_stmts: fix handling of copyback parameters	Tristan Gingold	2022-09-07	1	-20/+17
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-36/+49
*	synth/elab-vhdl_values: add Value_Terminal	Tristan Gingold	2022-07-25	1	-3/+21
*	elab-vhdl_values: add Create_Value_Quantity	Tristan Gingold	2022-07-16	1	-2/+23
*	synth-vhdl_stmts: handle alias in assignment expression	Tristan Gingold	2022-06-06	1	-0/+19
*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	1	-3/+27
*	elab-vhdl_objtypes: use value_offsets for record elements offset.	Tristan Gingold	2022-05-24	1	-1/+2
*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-18/+5
*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-23/+3
*	synth/elab-vhdl_values: use a proper type for signal_index	Tristan Gingold	2022-05-19	1	-1/+2
*	elab-vhdl_values.adb: fix a typo. Fix #1968	Tristan Gingold	2022-02-18	1	-2/+2
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-0/+500