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| author | Tristan Gingold <tgingold@free.fr> | 2022-02-18 06:39:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-02-18 06:39:24 +0100 |
| commit | 299333e4c12e27fa456a73fa0baeedd1f2f9ec30 (patch) | |
| tree | d9c178bb306335068a5d4b7cf7a026415c74d9b3 /src/synth/elab-vhdl_values.adb | |
| parent | 43f3ab99bf70faba67910b8051bfcca17fb3799a (diff) | |
| download | ghdl-299333e4c12e27fa456a73fa0baeedd1f2f9ec30.tar.gz ghdl-299333e4c12e27fa456a73fa0baeedd1f2f9ec30.tar.bz2 ghdl-299333e4c12e27fa456a73fa0baeedd1f2f9ec30.zip | |
elab-vhdl_values.adb: fix a typo. Fix #1968
Diffstat (limited to 'src/synth/elab-vhdl_values.adb')
| -rw-r--r-- | src/synth/elab-vhdl_values.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 90e72f223..017edc700 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -246,9 +246,9 @@ package body Elab.Vhdl_Values is Res.Val.Mem (I - 1) := Src.Val.Mem (I - 1); end loop; when Value_Net => - Res := (Src.Typ, Create_Value_Net (Src.Val.S)); + Res := (Src.Typ, Create_Value_Net (Src.Val.N)); when Value_Wire => - Res := (Src.Typ, Create_Value_Wire (Src.Val.S)); + Res := (Src.Typ, Create_Value_Wire (Src.Val.N)); when Value_File => Res := Create_Value_File (Src.Typ, Src.Val.File); when Value_Signal => |