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* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-172-13/+11
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-174-67/+18
* synth: handle protected types in subprogramsTristan Gingold2022-09-172-7/+50
* synth: improve file handling (skip extra data, errors)Tristan Gingold2022-09-173-3/+53
* synth: finalize filesTristan Gingold2022-09-173-4/+30
* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
* synth: preliminary work to factorize codeTristan Gingold2022-09-165-39/+64
* simul: handle active attributeTristan Gingold2022-09-163-1/+9
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
* synth: handle vhdl-87 filesTristan Gingold2022-09-151-0/+6
* synth: handle access subtypesTristan Gingold2022-09-151-0/+8
* synth: handle read for files of unconstrained arraysTristan Gingold2022-09-153-1/+54
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
* synth: detect overflow in static exponentiationTristan Gingold2022-09-141-3/+16
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-122-1/+8
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
* synth: fix and add checks for memory management.Tristan Gingold2022-09-1012-110/+328
* simul: add support for protected objectsTristan Gingold2022-09-089-20/+204
* elab-vhdl_objtypes: handle bounded array base type. Fix #2187Tristan Gingold2022-09-081-1/+2
* elab-vhdl_values: factorize codeTristan Gingold2022-09-075-27/+14
* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-073-26/+38
* elab-vhdl_stmts: fix a TODOTristan Gingold2022-09-071-1/+3
* synth: handle open entity aspectTristan Gingold2022-09-071-4/+4
* elab-vhdl_heap: fix handling of simple access typesTristan Gingold2022-09-071-4/+17
* synth: handle generics in blocksTristan Gingold2022-09-062-7/+32
* simul: add an hook to display report/assert messageTristan Gingold2022-09-062-36/+78
* synth-vhdl_eval: handle std_logic_signed and std_logic_unsignedTristan Gingold2022-09-061-55/+111
* synth: add evaluation for ieee.std_logic_arithTristan Gingold2022-09-056-43/+1181
* synth: extract synth-ieee-utils from synth-ieee-numeric_stdTristan Gingold2022-09-022-21/+46
* synth: improve debug subprogramsTristan Gingold2022-09-022-1/+8
* synth: use areapoolsTristan Gingold2022-09-0225-175/+839
* synth: factorize code for tracing statements executionTristan Gingold2022-09-023-13/+16
* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-251-4/+28
* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
* synth: handle type left/right attributesTristan Gingold2022-08-253-0/+26
* elab: add default value to portsTristan Gingold2022-08-234-13/+28
* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
* simul: rework assertions execution and error handlingTristan Gingold2022-08-213-2/+9
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-202-20/+22
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-192-6/+35
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