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* std_names: add Name_LocTristan Gingold2021-03-171-1/+2
* synth: handle pow and arctan from ieee.math_real. Fix #1665Tristan Gingold2021-02-271-6/+7
* std_names: add async_abort and sync_abort. For #1654Tristan Gingold2021-02-211-29/+31
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-7/+9
* std_names: add gclk. For #1610Tristan Gingold2021-01-251-1/+2
* update license headersumarcor2021-01-141-11/+9
* vhdl: recognize ieee.numeric_std_unsigned. For #1572Tristan Gingold2021-01-011-13/+14
* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-161-1/+3
* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-071-2/+4
* vhdl: add force and release tokens. For #1416Tristan Gingold2020-08-011-68/+68
* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-18/+21
* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-111-6/+7
* vhdl: handle pragma synthesis_on/synthesis_off.Tristan Gingold2020-04-111-1/+3
* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-1/+3
* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-221-16/+19
* std_names: add *_reduce names.Tristan Gingold2020-03-131-5/+11
* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-5/+6
* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-031-47/+51
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-11/+15
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-3/+4
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-3/+3
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-8/+9
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-1/+3
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-041-10/+11
* Add names for formal input gates/attributes.Tristan Gingold2019-10-301-1/+8
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-4/+6
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-2/+2
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-101-3/+4
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-071-3/+4
* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-3/+5
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-111-3/+5
* std_names: add std_matchTristan Gingold2019-08-301-3/+4
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-161-10/+10
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-133/+135
* vhdl: handle (discard) more pragmas.Tristan Gingold2019-07-251-1/+6
* vhdl scanner: handle pragma translate_on/translate_off.Tristan Gingold2019-07-241-1/+4
* vhdl: recognize resize function.Tristan Gingold2019-07-241-3/+4
* std_names: add names for math_real.Tristan Gingold2019-06-281-1/+4
* vhdl: recognize to_integer/to_signed/to_unsigned.Tristan Gingold2019-06-201-1/+4
* names: add more sv names.Tristan Gingold2019-05-111-39/+60
* std_names: add new names.Tristan Gingold2018-12-071-5/+16
* std_names: add identifiers from EDIF.Tristan Gingold2018-11-141-18/+50
* reorder names.Tristan Gingold2018-08-041-330/+458
* rework parse_expression to add parse_binary_expression.Tristan Gingold2018-08-041-101/+102
* std_names: add more keywords.Tristan Gingold2018-02-081-10/+13
* std_names: add localparam, trior, triand..Tristan Gingold2018-02-061-7/+14
* libraries: get rid of Nam_Buffer.Tristan Gingold2018-01-201-16/+17
* Preliminary support for tool directives.Tristan Gingold2017-11-061-1/+6
* Name_Last_Character: use usual notation.Tristan Gingold2017-10-051-3/+2
* textio: use grt.fcvt to write reals.Tristan Gingold2017-04-191-2/+3
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