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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:58:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:58:04 +0200 |
| commit | 167a6d0c0c9bdcc6381183e4913df7ccab03269e (patch) | |
| tree | 0d8b29079de198685f9699bcac68f78b8a8457ff /src/std_names.ads | |
| parent | cdda9d783f71a13fa2c828f6b8677f64932f6a6e (diff) | |
| download | ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.gz ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.bz2 ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.zip | |
vhdl: recognize to_bitvector.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index da13ace61..ff489c8bf 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -727,9 +727,10 @@ package Std_Names is Name_Shift_Right : constant Name_Id := Name_First_Ieee + 025; Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 028; - Name_Ceil : constant Name_Id := Name_First_Ieee + 029; - Name_Log2 : constant Name_Id := Name_First_Ieee + 030; + Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 029; + Name_Ceil : constant Name_Id := Name_First_Ieee + 030; + Name_Log2 : constant Name_Id := Name_First_Ieee + 031; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. |