| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul-vhdl_simul: add support for PSL directives | Tristan Gingold | 2022-08-20 | 1 | -10/+252 |
| * | simul: handle resolved signals (WIP) | Tristan Gingold | 2022-08-19 | 1 | -42/+295 |
| * | ghdlsimul: add an option to debug before elaboration | Tristan Gingold | 2022-08-18 | 1 | -3/+3 |
| * | simul: handle individual associations | Tristan Gingold | 2022-08-17 | 1 | -2/+9 |
| * | simul: add create_connects | Tristan Gingold | 2022-08-17 | 1 | -1/+92 |
| * | simul: create terminals (WIP) | Tristan Gingold | 2022-08-17 | 1 | -6/+49 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+1992 |
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index : iCE40/ghdl | |
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