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simul
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simul-vhdl_elab.ads
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Author
Age
Files
Lines
*
simul: refactoring, expose more subprograms
Tristan Gingold
2023-02-04
1
-0
/
+8
*
simul: fix handling of drivers/sensitivity within processes
Tristan Gingold
2023-01-12
1
-10
/
+1
*
simul: fix signal attribute or guard as actual in connections
Tristan Gingold
2022-10-06
1
-1
/
+3
*
simul: factorize code, add sub_signal_type
Tristan Gingold
2022-09-29
1
-10
/
+6
*
simul: gather disconnection specifications, create guard signal
Tristan Gingold
2022-09-25
1
-0
/
+17
*
simul: handle more signals types
Tristan Gingold
2022-09-15
1
-0
/
+3
*
simul: factorize code to compute number of sources
Tristan Gingold
2022-08-23
1
-0
/
+9
*
simul: add extra drivers for ports without sources
Tristan Gingold
2022-08-23
1
-0
/
+11
*
simul: handle resolved signals (WIP)
Tristan Gingold
2022-08-19
1
-1
/
+2
*
simul: add create_connects
Tristan Gingold
2022-08-17
1
-6
/
+12
*
simul: create terminals (WIP)
Tristan Gingold
2022-08-17
1
-0
/
+10
*
simul: gather terminals
Tristan Gingold
2022-07-25
1
-0
/
+14
*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
1
-0
/
+200