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author | Tristan Gingold <tgingold@free.fr> | 2022-09-29 06:38:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-09-29 22:02:32 +0200 |
commit | 9e29eca1eb46cb6d3fabe9ab458ba77610823612 (patch) | |
tree | 6abd86da085185deb61366b25e64bd7bf0ab475a /src/simul/simul-vhdl_elab.ads | |
parent | f247d3eaa1d2dda3eb26e038efe52b0c6cbfd754 (diff) | |
download | ghdl-9e29eca1eb46cb6d3fabe9ab458ba77610823612.tar.gz ghdl-9e29eca1eb46cb6d3fabe9ab458ba77610823612.tar.bz2 ghdl-9e29eca1eb46cb6d3fabe9ab458ba77610823612.zip |
simul: factorize code, add sub_signal_type
Diffstat (limited to 'src/simul/simul-vhdl_elab.ads')
-rw-r--r-- | src/simul/simul-vhdl_elab.ads | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/simul/simul-vhdl_elab.ads b/src/simul/simul-vhdl_elab.ads index 233bad313..aff66472a 100644 --- a/src/simul/simul-vhdl_elab.ads +++ b/src/simul/simul-vhdl_elab.ads @@ -89,7 +89,7 @@ package Simul.Vhdl_Elab is type Connect_Index_Type is new Nat32; No_Connect_Index : constant Connect_Index_Type := 0; - type Connect_Endpoint is record + type Sub_Signal_Type is record Base : Signal_Index_Type; Offs : Value_Offsets; Typ : Type_Acc; @@ -98,11 +98,11 @@ package Simul.Vhdl_Elab is -- Connections. For each associations (block/component/entry), the -- elaborator adds an entry in that table. type Connect_Entry is record - Formal : Connect_Endpoint; + Formal : Sub_Signal_Type; -- Next connection for the formal. Formal_Link : Connect_Index_Type; - Actual : Connect_Endpoint; + Actual : Sub_Signal_Type; -- Next connection for the actual. Actual_Link : Connect_Index_Type; @@ -168,7 +168,7 @@ package Simul.Vhdl_Elab is when Mode_Quiet | Mode_Stable | Mode_Delayed | Mode_Transaction => Time : Std_Time; - Prefix : Memory_Ptr; + Pfx : Sub_Signal_Type; when Mode_Above => null; when Mode_Guard => @@ -187,9 +187,7 @@ package Simul.Vhdl_Elab is type Driver_Entry is record -- The signal having a driver. - Sig : Signal_Index_Type; - Off : Value_Offsets; - Typ : Type_Acc; + Sig : Sub_Signal_Type; -- Previous driver for the same signal. Prev_Sig : Driver_Index_Type; @@ -214,9 +212,7 @@ package Simul.Vhdl_Elab is Table_Initial => 128); type Disconnect_Entry is record - Sig : Signal_Index_Type; - Off : Value_Offsets; - Typ : Type_Acc; + Sig : Sub_Signal_Type; Prev : Disconnect_Index_Type; Val : Std_Time; end record; |