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author | Tristan Gingold <tgingold@free.fr> | 2022-07-25 05:17:10 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-07-25 05:17:10 +0200 |
commit | 9113c965378a69447386d57d6d8a9f4caf7d1581 (patch) | |
tree | a8bc0ffe9324fe1273fe10750764664f786ffb53 /src/simul/simul-vhdl_elab.ads | |
parent | 54cf60d44d1110b127f6a81ee789eef4740630a1 (diff) | |
download | ghdl-9113c965378a69447386d57d6d8a9f4caf7d1581.tar.gz ghdl-9113c965378a69447386d57d6d8a9f4caf7d1581.tar.bz2 ghdl-9113c965378a69447386d57d6d8a9f4caf7d1581.zip |
simul: gather terminals
Diffstat (limited to 'src/simul/simul-vhdl_elab.ads')
-rw-r--r-- | src/simul/simul-vhdl_elab.ads | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.ads b/src/simul/simul-vhdl_elab.ads index c8bc54e94..795df7245 100644 --- a/src/simul/simul-vhdl_elab.ads +++ b/src/simul/simul-vhdl_elab.ads @@ -197,4 +197,18 @@ package Simul.Vhdl_Elab is Table_Index_Type => Quantity_Index_Type, Table_Low_Bound => No_Quantity_Index + 1, Table_Initial => 128); + + type Terminal_Entry is record + Decl : Iir; + Inst : Synth_Instance_Acc; + Across_Typ : Type_Acc; + Through_Typ : Type_Acc; + Ref_Val : Memory_Ptr; + end record; + + package Terminal_Table is new Tables + (Table_Component_Type => Terminal_Entry, + Table_Index_Type => Terminal_Index_Type, + Table_Low_Bound => No_Terminal_Index + 1, + Table_Initial => 32); end Simul.Vhdl_Elab; |