| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul: factorize code to compute number of sources | Tristan Gingold | 2022-08-23 | 1 | -0/+35 |
| * | simul: add extra drivers for ports without sources | Tristan Gingold | 2022-08-23 | 1 | -10/+76 |
| * | simul: handle individual associations | Tristan Gingold | 2022-08-17 | 1 | -2/+7 |
| * | simul: add create_connects | Tristan Gingold | 2022-08-17 | 1 | -37/+38 |
| * | simul: create terminals (WIP) | Tristan Gingold | 2022-08-17 | 1 | -1/+2 |
| * | simul: gather terminals | Tristan Gingold | 2022-07-25 | 1 | -0/+29 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+677 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |