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author | Tristan Gingold <tgingold@free.fr> | 2022-08-17 02:28:54 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-08-17 02:28:54 +0200 |
commit | e57ba3e335d1f3692805f46d7d9cba49ffea4219 (patch) | |
tree | 6cfbe15ad39389ea98c98ffdd14c442119f8c587 /src/simul/simul-vhdl_elab.adb | |
parent | a1f5a8797f36e68a3ca61568a25db67e29fda613 (diff) | |
download | ghdl-e57ba3e335d1f3692805f46d7d9cba49ffea4219.tar.gz ghdl-e57ba3e335d1f3692805f46d7d9cba49ffea4219.tar.bz2 ghdl-e57ba3e335d1f3692805f46d7d9cba49ffea4219.zip |
simul: create terminals (WIP)
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
-rw-r--r-- | src/simul/simul-vhdl_elab.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index f3ca2ff87..884d83c28 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -102,7 +102,8 @@ package body Simul.Vhdl_Elab is Across_Typ := Get_Subtype_Object (Inst, Get_Across_Type (Def)); Through_Typ := Get_Subtype_Object (Inst, Get_Through_Type (Def)); pragma Assert (Val.Val.T = No_Terminal_Index); - Terminal_Table.Append ((Decl, Inst, Across_Typ, Through_Typ, null)); + Terminal_Table.Append ((Decl, Inst, Across_Typ, Through_Typ, null, + No_Scalar_Quantity, No_Scalar_Terminal)); Val.Val.T := Terminal_Table.Last; end Gather_Terminal; |