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* simul: simplify codeTristan Gingold2022-08-232-16/+7
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
* elab: add default value to portsTristan Gingold2022-08-234-13/+28
* grt-signals: add ghdl_signal_add_extra_driverTristan Gingold2022-08-232-0/+19
* grt-signals: internal refactoring for drivers creationTristan Gingold2022-08-221-25/+39
* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-212-40/+51
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
* grt-errors: remove error_hook (was unused)Tristan Gingold2022-08-212-14/+0
* simul: rework assertions execution and error handlingTristan Gingold2022-08-215-10/+13
* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
* simul: handle after clauses in signal assignmentTristan Gingold2022-08-213-70/+111
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-204-34/+289
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-194-49/+332
* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-183-3/+6
* testsuite/gna: add a test and close #2179Tristan Gingold2022-08-182-0/+48
* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
* simul: add create_connectsTristan Gingold2022-08-174-46/+144
* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
* suite_driver: avoid spurious error messages, fix --list-filesTristan Gingold2022-08-161-2/+2
* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
* testsuite/synth: add more tests for memoryTristan Gingold2022-08-165-0/+217
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
* psl-rewrites: minor style changeTristan Gingold2022-08-161-2/+1
* gdbinit: add ppsltfTristan Gingold2022-08-151-0/+8
* vhdl-prints: improve handling of PSL. For #2178Tristan Gingold2022-08-156-63/+184
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-1514-438/+505
* pyGHDL: update bindingsTristan Gingold2022-08-151-201/+203
* testsuite/synth: add a test for #2177Tristan Gingold2022-08-145-0/+2768
* elab-vhdl_values-debug: improve output of debug_valtypTristan Gingold2022-08-141-1/+3
* synth-vhdl_context: fix handling of alias in get_net. Fix #2177Tristan Gingold2022-08-141-4/+3
* testsuite/synth: add a test for #2176Tristan Gingold2022-08-142-0/+30
* vhdl: recognize log10 and sqrt from math_real. Fix #2176Tristan Gingold2022-08-144-10/+32
* testsuite/synth: add a test for previous commitTristan Gingold2022-08-143-1/+82
* synth: handle assignment to record aggregateTristan Gingold2022-08-142-31/+109
* testsuite/synth: rename mem2d01 to memdp01Tristan Gingold2022-08-1410-0/+0
* testsuite/synth: add a test for #2077Tristan Gingold2022-08-142-1/+47
* netlists-memories: improve checks to avoid the crash of #2077Tristan Gingold2022-08-141-32/+75
* testsuite/synth: add tests for #2077Tristan Gingold2022-08-142-0/+86
* testsuite/synth: add tests for #2077Tristan Gingold2022-08-137-0/+268
* netlists-memories: fix a crash on multi-dim memories. For #2077Tristan Gingold2022-08-131-3/+6
* testsuite/gna: add a test for #2166Tristan Gingold2022-08-122-0/+26
* trans-chap3: fix invalid copy of element layout. For #2166Tristan Gingold2022-08-121-2/+4
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