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authorTristan Gingold <tgingold@free.fr>2023-01-03 13:53:37 +0100
committerTristan Gingold <tgingold@free.fr>2023-01-03 16:47:28 +0100
commit1e5f96642bbf470934f245c98908337f75abb35a (patch)
tree32c6a26b31a4e27e7306ac7c9faa7159d65010a9 /src/simul
parentd7ffe048ed623283655a11ffc5e75d6e5731f738 (diff)
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synth: introduce type_array_unbounded
Diffstat (limited to 'src/simul')
-rw-r--r--src/simul/simul-vhdl_debug.adb1
-rw-r--r--src/simul/simul-vhdl_elab.adb1
-rw-r--r--src/simul/simul-vhdl_simul.adb2
3 files changed, 4 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb
index 8eb2c1cab..fe49e2292 100644
--- a/src/simul/simul-vhdl_debug.adb
+++ b/src/simul/simul-vhdl_debug.adb
@@ -315,6 +315,7 @@ package body Simul.Vhdl_Debug is
end;
when Type_Unbounded_Vector
| Type_Unbounded_Record
+ | Type_Array_Unbounded
| Type_Unbounded_Array
| Type_Slice
| Type_Protected
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 229c75c77..8480432a6 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -123,6 +123,7 @@ package body Simul.Vhdl_Elab is
when Type_Slice
| Type_Access
+ | Type_Array_Unbounded
| Type_Unbounded_Vector
| Type_Unbounded_Array
| Type_Unbounded_Record
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 354ca062f..37fd14d69 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -2576,6 +2576,7 @@ package body Simul.Vhdl_Simul is
when Type_Slice
| Type_Access
+ | Type_Array_Unbounded
| Type_Unbounded_Vector
| Type_Unbounded_Array
| Type_Unbounded_Record
@@ -2739,6 +2740,7 @@ package body Simul.Vhdl_Simul is
when Type_Slice
| Type_Access
+ | Type_Array_Unbounded
| Type_Unbounded_Vector
| Type_Unbounded_Array
| Type_Unbounded_Record