aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
* testsuite/synth: add a test for #938Tristan Gingold2021-12-064-0/+109
* synth: add --latches option to enable latches. Fix #938Tristan Gingold2021-12-063-1/+11
* Update .editorconfig with settings for Ada filesstd-max2021-12-061-0/+4
* testsuite/gna: add a test for conformance rulesTristan Gingold2021-12-032-0/+24
* vhdl-sem.adb: fix incorrect check for conformance rulesTristan Gingold2021-12-031-1/+3
* testsuite/synth: add a test for #1926Tristan Gingold2021-11-293-0/+485
* synth/elab-vhdl_expr: handle slices and indexed names. Fix #1926Tristan Gingold2021-11-291-19/+11
* testsuite/synth: avoid use of verilog identifiersTristan Gingold2021-11-286-20/+20
* synth memories: also accept constant signal as memory initial valueTristan Gingold2021-11-282-4/+9
* elab-vhdl_objtypes.adb: add an assertionTristan Gingold2021-11-281-0/+2
* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
* synth: adjustments for foreign_moduleTristan Gingold2021-11-282-3/+12
* synth: add a hook to resolve foreign instantiation namesTristan Gingold2021-11-282-0/+8
* synth-vhdl_insts.adb: split synth_Instantiate_ModuleTristan Gingold2021-11-281-14/+26
* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-2810-32/+108
* vhdl-parse: improve error message for empty recordsTristan Gingold2021-11-281-29/+33
* testsuite/gna: add test from #1924Tristan Gingold2021-11-274-0/+100
* testsuite/gna: add a test for #1914Tristan Gingold2021-11-246-0/+204
* vhdl/translate: handle target aggregate with unbounded names. Fix #1914Tristan Gingold2021-11-244-22/+75
* testsuite/gna: add a test for #1919Tristan Gingold2021-11-213-0/+22
* vhdl-sem_decls: avoid a crash on invalid alias name. Fix #1919Tristan Gingold2021-11-211-0/+10
* testsuite/synth: add a test for #1920Tristan Gingold2021-11-213-0/+68
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: put direction into port descTristan Gingold2021-11-178-31/+30
* synth: use a global table for instances attributesTristan Gingold2021-11-176-168/+117
* synth: renaming to instance_attributes.Tristan Gingold2021-11-1711-66/+72
* synth/netlists-disp_verilog: display port attributesTristan Gingold2021-11-171-18/+42
* synth: add ports attributesTristan Gingold2021-11-173-0/+120
* vhdl-utils.adb: minor refactoringTristan Gingold2021-11-171-7/+3
* grt: refactoring to fix build failure. For #1913Tristan Gingold2021-11-175-394/+443
* Add commentsTristan Gingold2021-11-172-0/+4
* vhdl-evaluation: use grt to compute value attribute for integers.Tristan Gingold2021-11-173-33/+97
* grt/Makefile.inc: add a dependency for grt-cgnatrts.Tristan Gingold2021-11-161-2/+3
* testsuite/synth: add a test for #1912Tristan Gingold2021-11-162-0/+82
* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-162-15/+110
* testsuite/gna: add scripts to generate 1d/2d aggregatesTristan Gingold2021-11-162-0/+30
* testsuite/gna: add a test for #1913Tristan Gingold2021-11-152-0/+123
* vhdl-evaluation: catch bad parameter for value attribute. Fix #1913Tristan Gingold2021-11-151-1/+7
* testsuite/gna: add a test for previous commitTristan Gingold2021-11-154-0/+83
* vhdl-sem_expr: improve code generation for multi-dim aggregatesTristan Gingold2021-11-151-3/+3
* testsuite/synth: add a test for syn_black_boxTristan Gingold2021-11-132-0/+23
* synth: handle syn_black_box attribute in vhdl architecturesTristan Gingold2021-11-131-10/+75
* testsuite/synth: add a test for #1911Tristan Gingold2021-11-133-0/+315
* synth: add exec_name_subtype. Fix #1911Tristan Gingold2021-11-133-4/+52
* testsuite/synth: add a test for black boxesTristan Gingold2021-11-124-0/+80
* testsuite/synth: adjust test after previous commitTristan Gingold2021-11-124-2/+20
* synth: do not display black boxesTristan Gingold2021-11-121-1/+6
* std_names: add syn_black_boxTristan Gingold2021-11-123-182/+185
* testsuite/synth: add tests for rol/ror. For #1909Tristan Gingold2021-11-115-1/+85
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 12:14:49 +0000