testsuite/synth: avoid use of verilog identifiers

6 files changed, 20 insertions, 20 deletions

diff --git a/testsuite/synth/issue1090/simple_ram.vhdl b/testsuite/synth/issue1090/simple_ram.vhdl
index 345083850..99187a681 100644
--- a/testsuite/synth/issue1090/simple_ram.vhdl
+++ b/testsuite/synth/issue1090/simple_ram.vhdl
@@ -35,11 +35,11 @@ entity simple_ram is
 
     en : in std_logic;
     raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
-    do : out std_logic_vector(31 downto 0);
+    dout : out std_logic_vector(31 downto 0);
 
     we : in std_logic_vector(3 downto 0);
     waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
-    di : in std_logic_vector(31 downto 0)
+    din : in std_logic_vector(31 downto 0)
     );
 end simple_ram;
 
@@ -55,19 +55,19 @@ begin
   begin
     if clk'event and clk = '1' and en = '1' then -- Unsupported: clock enable
       if we(3) = '1' then
-        ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24);
+        ram(to_integer(unsigned(waddr)))(31 downto 24) <= din(31 downto 24);
       end if;
       if we(2) = '1' then
-        ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16);
+        ram(to_integer(unsigned(waddr)))(23 downto 16) <= din(23 downto 16);
       end if;
       if we(1) = '1' then
-        ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 );
+        ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= din(15 downto 8 );
       end if;
       if we(0) = '1' then
-        ram(to_integer(unsigned(waddr)))(7  downto 0 ) <= di(7  downto 0 );
+        ram(to_integer(unsigned(waddr)))(7  downto 0 ) <= din(7  downto 0 );
       end if;
       read := ram(to_integer(unsigned(raddr)));
-      do <= read;
+      dout <= read;
     end if;
   end process;
 end behavioral;
diff --git a/testsuite/synth/issue1090/tb_simple_ram.vhdl b/testsuite/synth/issue1090/tb_simple_ram.vhdl
index 437c6543a..e5f515c21 100644
--- a/testsuite/synth/issue1090/tb_simple_ram.vhdl
+++ b/testsuite/synth/issue1090/tb_simple_ram.vhdl
@@ -15,8 +15,8 @@ architecture behav of tb_simple_ram is
 begin
   dut: entity work.simple_ram
     port map (clk => clk,
-              en => en, raddr => raddr, do => rdat,
-              we => we, waddr => waddr, di => wdat);
+              en => en, raddr => raddr, dout => rdat,
+              we => we, waddr => waddr, din => wdat);
 
   process
     procedure pulse is
diff --git a/testsuite/synth/issue1107/unconnected.vhdl b/testsuite/synth/issue1107/unconnected.vhdl
index 0c7886a24..d8dcd2a10 100644
--- a/testsuite/synth/issue1107/unconnected.vhdl
+++ b/testsuite/synth/issue1107/unconnected.vhdl
@@ -4,12 +4,12 @@ use ieee.std_logic_1164.all;
 
 entity unconnected is
   port (
-    output: out std_logic
+    outp: out std_logic
     );
 end entity;
 
 architecture arch of unconnected is
   signal no_value: std_logic;
 begin
-  output <= no_value;
+  outp <= no_value;
 end;
diff --git a/testsuite/synth/issue1133/foo.vhdl b/testsuite/synth/issue1133/foo.vhdl
index 32a972cda..95dcddf55 100644
--- a/testsuite/synth/issue1133/foo.vhdl
+++ b/testsuite/synth/issue1133/foo.vhdl
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity foo is
   port (
-    input        : in std_logic_vector(7 downto 0);
+    inp        : in std_logic_vector(7 downto 0);
     output_ok    : out std_logic_vector(7 downto 0);
     output_error : out std_logic_vector(7 downto 0)
   );
@@ -16,9 +16,9 @@ architecture foo of foo is
 begin
 
   -- This works fine
-  null_vector  <= input(null_vector'range);
+  null_vector  <= inp(null_vector'range);
   output_ok    <= null_vector & (7 downto 0 => '0');
   -- This doesn't
-  output_error <= input(-1 downto 0) & (7 downto 0 => '0');
+  output_error <= inp(-1 downto 0) & (7 downto 0 => '0');
 
 end foo;
diff --git a/testsuite/synth/issue1909/reproducebug.vhdl b/testsuite/synth/issue1909/reproducebug.vhdl
index 60655b0eb..940ca41ce 100644
--- a/testsuite/synth/issue1909/reproducebug.vhdl
+++ b/testsuite/synth/issue1909/reproducebug.vhdl
@@ -5,8 +5,8 @@ library ieee;
 entity ReproduceBug is
   port(
     clk      : in std_logic;
-    input    : in unsigned(7 downto 0);
-    output   : out unsigned(7 downto 0)
+    inp    : in unsigned(7 downto 0);
+    outp   : out unsigned(7 downto 0)
   );
 end ReproduceBug;
 
@@ -18,7 +18,7 @@ begin
   Main: process(clk)
   begin
     if rising_edge(Clk) then
-      output <= input ror 1; -- can also be 'rol'
+      outp <= inp ror 1; -- can also be 'rol'
     end if;
   end process;
 
diff --git a/testsuite/synth/issue955/ent1.vhdl b/testsuite/synth/issue955/ent1.vhdl
index 68c0f9c06..0e4ff0697 100644
--- a/testsuite/synth/issue955/ent1.vhdl
+++ b/testsuite/synth/issue955/ent1.vhdl
@@ -11,15 +11,15 @@ end ent1;
 architecture a of ent1 is
     type reg_t is array(0 to 7) of std_logic_vector(0 to 7);
 
-    signal reg : reg_t := (x"10", x"11", x"12", x"13",
+    signal reg1 : reg_t := (x"10", x"11", x"12", x"13",
                            x"14", x"15", x"16", x"17");
 begin
     process(clk)
     begin
         if rising_edge(clk) then
-            reg <= reg(1 to 7) & x"00";
+            reg1 <= reg1(1 to 7) & x"00";
         end if;
     end process;
 
-    o <= reg (0);
+    o <= reg1 (0);
 end;