testsuite/gna: add a test for #1914

6 files changed, 204 insertions, 0 deletions

diff --git a/testsuite/gna/issue1914/delayline.vhdl b/testsuite/gna/issue1914/delayline.vhdl
new file mode 100644
index 000000000..0e43cf330
--- /dev/null
+++ b/testsuite/gna/issue1914/delayline.vhdl
@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity delayline is
+    generic (
+        delay : positive
+    );
+    port (
+        clk   : in std_logic;
+        i     : in std_logic_vector;
+        o     : out std_logic_vector
+    );
+end entity;
+
+architecture rtl of delayline is
+    type delay_t is array (natural range <>) of std_logic_vector;
+    signal d : delay_t(delay - 1 downto 0)(i'range); -- This statement causes the problem
+begin
+    assert i'length = o'length
+        report "i and o length should be equal"
+        severity error;
+
+    (o, d) <= d & i when rising_edge(clk);
+
+end architecture rtl;
diff --git a/testsuite/gna/issue1914/delayline1d.vhdl b/testsuite/gna/issue1914/delayline1d.vhdl
new file mode 100644
index 000000000..e5d79c01c
--- /dev/null
+++ b/testsuite/gna/issue1914/delayline1d.vhdl
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity delayline1d is
+    generic (
+        delay : positive
+    );
+    port (
+        clk   : in std_logic;
+        i     : in std_logic;
+        o     : out std_logic
+    );
+end entity;
+
+architecture rtl of delayline1d is
+    signal d : std_logic_vector(delay - 1 downto 0);
+begin
+    (o, d) <= d & i when rising_edge(clk);
+
+end architecture rtl;
diff --git a/testsuite/gna/issue1914/tb_delayline-orig.vhdl b/testsuite/gna/issue1914/tb_delayline-orig.vhdl
new file mode 100644
index 000000000..5526f2277
--- /dev/null
+++ b/testsuite/gna/issue1914/tb_delayline-orig.vhdl
@@ -0,0 +1,50 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+
+entity tb_delayline is
+    generic (
+       delay : natural := 10;
+       runner_cfg : string
+    );
+end entity;
+
+architecture rtl of tb_delayline is
+    signal clk : std_logic := '0';
+    signal i, o : std_logic_vector(7 downto 0);
+begin
+
+    -- Runner setup and timeout time
+    test_runner_setup(runner, runner_cfg);
+    test_runner_watchdog(runner, 10 ms);
+    
+    -- 100 Mhz clock
+    clk <= not clk after 5 ns;
+
+    -- Test Start
+    process
+    begin
+        while test_suite loop     
+            if run("test") then
+                check_equal(1, 1, "yay");
+            end if;
+        end loop;
+        test_runner_cleanup(runner);
+        wait;
+    end process;
+
+
+    -- Device Under Test 
+    c0: entity work.delayline(rtl)
+        generic map (
+            delay => delay
+        )
+        port map (
+            clk => clk,
+            i => i, 
+            o => o
+        );
+end architecture;
+
diff --git a/testsuite/gna/issue1914/tb_delayline.vhdl b/testsuite/gna/issue1914/tb_delayline.vhdl
new file mode 100644
index 000000000..4d6e9b7b1
--- /dev/null
+++ b/testsuite/gna/issue1914/tb_delayline.vhdl
@@ -0,0 +1,56 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_delayline is
+    generic (
+       delay : natural := 10
+    );
+end entity;
+
+architecture rtl of tb_delayline is
+    signal clk : std_logic := '0';
+    signal i, o : std_logic_vector(7 downto 0);
+begin
+
+  -- 100 Mhz clock
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end pulse;
+  begin
+    for j in 1 to 9 loop
+      i <= std_logic_vector(to_unsigned (j + 16 * (15 - j), 8));
+      pulse;
+    end loop;
+
+    i <= x"f0";
+    pulse;
+    i <= x"1e";
+    for j in 1 to 9 loop
+      pulse;
+      assert o = std_logic_vector(to_unsigned (j + 16 * (15 - j), 8))
+        severity failure;
+    end loop;
+    pulse;
+    assert o = x"f0" severity failure;
+    report "Test is ok";
+    wait;
+  end process;
+
+    -- Device Under Test
+    c0: entity work.delayline(rtl)
+        generic map (
+            delay => delay
+        )
+        port map (
+            clk => clk,
+            i => i,
+            o => o
+        );
+end architecture;
+
diff --git a/testsuite/gna/issue1914/tb_delayline1d.vhdl b/testsuite/gna/issue1914/tb_delayline1d.vhdl
new file mode 100644
index 000000000..3689851f4
--- /dev/null
+++ b/testsuite/gna/issue1914/tb_delayline1d.vhdl
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity tb_delayline1d is
+    generic (
+       delay : natural := 10
+    );
+end entity;
+
+architecture rtl of tb_delayline1d is
+    signal clk : std_logic := '0';
+    signal i, o : std_logic;
+begin
+
+  -- 100 Mhz clock
+  process
+  begin
+    for k in 1 to 5 loop
+      clk <= not clk;
+      wait for 5 ns;
+    end loop;
+    wait;
+  end process;
+
+    -- Device Under Test
+    c0: entity work.delayline1d(rtl)
+        generic map (
+            delay => delay
+        )
+        port map (
+            clk => clk,
+            i => i,
+            o => o
+        );
+end architecture;
+
diff --git a/testsuite/gna/issue1914/testsuite.sh b/testsuite/gna/issue1914/testsuite.sh
new file mode 100755
index 000000000..488f6fc7f
--- /dev/null
+++ b/testsuite/gna/issue1914/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+analyze delayline1d.vhdl tb_delayline1d.vhdl
+elab_simulate tb_delayline1d
+
+clean
+
+analyze delayline.vhdl tb_delayline.vhdl
+elab_simulate tb_delayline
+
+clean
+
+echo "Test successful"