aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* Install `std.standard` package VHDL sourceTorsten Maehne2019-05-011-0/+4
* update(doc)1138-4EB2019-04-3010-283/+393
* configure: use default_pic instead of default_pie.Tristan Gingold2019-04-273-9/+10
* do not hijack default_pieumarcor2019-04-271-2/+6
* add configure option to enable default_pieumarcor2019-04-274-28/+28
* Add testcase for vhpidirect.Tristan Gingold2019-04-273-0/+35
* vhdl: supports VHPIDIRECT in mcode backend.Tristan Gingold2019-04-2714-99/+473
* grt: add grt-dynload.adsTristan Gingold2019-04-271-0/+39
* translation: adjust scan of vhpidirect string.Tristan Gingold2019-04-271-6/+5
* trans-chap12: minor rewrite.Tristan Gingold2019-04-271-1/+3
* grt: rename grt-dynload.[ch] to grt-cdynload.[ch]Tristan Gingold2019-04-275-6/+6
* preserve externally set OPT_FLAGS, ADA_FLAGS and/or LIB_CFLAGSumarcor2019-04-251-3/+3
* libraries: rename _body files.Tristan Gingold2019-04-249-18/+18
* add some version to grt.ver (#800)umarcor2019-04-241-1/+1
* grt: update windows targets.psm1 with grt-dynload.Tristan Gingold2019-04-241-0/+2
* grt: extract grt-dynload from grt-cvpiTristan Gingold2019-04-246-62/+82
* [PATCH] synth: add comments.Tristan Gingold2019-04-182-6/+19
* synth: improve generation of aggregates.Tristan Gingold2019-04-162-14/+62
* synth: ignore component instantiations (TODO).Tristan Gingold2019-04-161-0/+4
* synth: minimal support of slices.Tristan Gingold2019-04-162-0/+88
* synth: add testcase for previous commit.Tristan Gingold2019-04-162-0/+25
* synth: handle synchronous enable in inference.Tristan Gingold2019-04-161-23/+45
* synth-expr: handle others in aggregate.Tristan Gingold2019-04-161-0/+5
* synth: handle free instances in net iterator.Tristan Gingold2019-04-161-4/+9
* testsuite: add dff01 tests.Tristan Gingold2019-04-165-0/+90
* testenv: add synth command.Tristan Gingold2019-04-161-0/+6
* synth: support async reset in inference.Tristan Gingold2019-04-162-95/+117
* synth: add adff, iadff.Tristan Gingold2019-04-162-0/+74
* synth: add --disp-noinlineTristan Gingold2019-04-163-6/+31
* synth: add comments.Tristan Gingold2019-04-164-21/+108
* simul: do not reverse the list twice; renaming.Tristan Gingold2019-04-161-24/+16
* Add reproducer for #797Tristan Gingold2019-04-155-0/+148
* vhdl: fix crash on access subtype. Fix #797Tristan Gingold2019-04-151-1/+2
* Add reproducer for #794Tristan Gingold2019-04-082-0/+90
* vhdl: fix crash for -Wdelayed-checks. Fix #794Tristan Gingold2019-04-081-1/+2
* Add reproducer for issue #791Tristan Gingold2019-04-063-0/+40
* vhdl: handle interface procedure for purity checks. Fix #791Tristan Gingold2019-04-061-0/+3
* Add testcase for previous commit.Tristan Gingold2019-04-063-0/+31
* vhdl: improve error message for EOF in readline.Tristan Gingold2019-04-061-0/+5
* Add testcase for #792Tristan Gingold2019-04-062-0/+35
* vhdl: adjust missing port association check. Fix #792Tristan Gingold2019-04-063-42/+41
* vendors: update scripts for uvvm.Tristan Gingold2019-03-303-288/+89
* gcc/Make-lang.in: do not enable warnings as errors.Tristan Gingold2019-03-261-1/+1
* Add testcase for #787Tristan Gingold2019-03-252-0/+25
* trans-chap8: adjust condition.Tristan Gingold2019-03-251-1/+3
* move algos to grt.Tristan Gingold2019-03-205-9/+12
* README: mention UVVM.Tristan Gingold2019-03-191-1/+1
* Add testcase for #736Tristan Gingold2019-03-154-0/+183
* vhdl: do not clear original node in canon for conditional signal assignment.Tristan Gingold2019-03-151-6/+9
* Add testcase for #779Tristan Gingold2019-03-142-0/+75
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 18:49:13 +0000