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| author | Tristan Gingold <tgingold@free.fr> | 2019-05-10 06:58:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-10 18:14:47 +0200 |
| commit | db7d0b337e85c3b327efa799418ef92de3a369ce (patch) | |
| tree | b1aec6a72ccf989da9617cbc0f581b12eb80b8c8 | |
| parent | 2c5ce4b3aab14d67e97623e8dfe31cf27a043e7c (diff) | |
| download | ghdl-db7d0b337e85c3b327efa799418ef92de3a369ce.tar.gz ghdl-db7d0b337e85c3b327efa799418ef92de3a369ce.tar.bz2 ghdl-db7d0b337e85c3b327efa799418ef92de3a369ce.zip | |
vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.
35 files changed, 310 insertions, 313 deletions
diff --git a/src/ghdldrv/ghdlxml.adb b/src/ghdldrv/ghdlxml.adb index 115f86d57..c55e0c30e 100644 --- a/src/ghdldrv/ghdlxml.adb +++ b/src/ghdldrv/ghdlxml.adb @@ -362,8 +362,8 @@ package body Ghdlxml is Put_Field (F, Image_Iir_Mode (Get_Iir_Mode (N, F))); when Type_Iir_Index32 => Put_Field (F, Iir_Index32'Image (Get_Iir_Index32 (N, F))); - when Type_Iir_Int64 => - Put_Field (F, Iir_Int64'Image (Get_Iir_Int64 (N, F))); + when Type_Int64 => + Put_Field (F, Int64'Image (Get_Int64 (N, F))); when Type_Boolean => Put_Field (F, Image_Boolean (Get_Boolean (N, F))); when Type_Iir_Staticness => @@ -398,8 +398,8 @@ package body Ghdlxml is (F, Strip (Iir_Int32'Image (Get_Iir_Int32 (N, F)))); when Type_Int32 => Put_Field (F, Strip (Int32'Image (Get_Int32 (N, F)))); - when Type_Iir_Fp64 => - Put_Field (F, Iir_Fp64'Image (Get_Iir_Fp64 (N, F))); + when Type_Fp64 => + Put_Field (F, Fp64'Image (Get_Fp64 (N, F))); when Type_Time_Stamp_Id => Put_Field (F, Image_Time_Stamp_Id (Get_Time_Stamp_Id (N, F))); diff --git a/src/types.ads b/src/types.ads index 2c59f583b..49eafa9a0 100644 --- a/src/types.ads +++ b/src/types.ads @@ -29,6 +29,10 @@ package Types is type Int32 is range -2**31 .. 2**31 - 1; for Int32'Size use 32; + -- 64 bits integer. + type Int64 is range -2**63 .. 2**63 - 1; + for Int64'Size use 64; + subtype Nat32 is Int32 range 0 .. Int32'Last; subtype Pos32 is Nat32 range 1 .. Nat32'Last; @@ -39,18 +43,6 @@ package Types is type Fp64 is new Interfaces.IEEE_Float_64; - -- iir_int32 is aimed at containing integer literal values. - type Iir_Int32 is new Interfaces.Integer_32; - - -- iir_int64 is aimed at containing units values. - type Iir_Int64 is new Interfaces.Integer_64; - - -- iir_fp64 is aimed at containing floating point values. - subtype Iir_Fp64 is Fp64; - - -- iir_index32 is aimed at containing an array index. - type Iir_Index32 is new Nat32; - -- Useful types. type String_Acc is access String; type String_Cst is access constant String; diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index a9411d62f..91b506e72 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -19,6 +19,7 @@ with Ada.Unchecked_Conversion; with Ada.Text_IO; use Ada.Text_IO; with System; +with Types; use Types; with Grt.Types; use Grt.Types; with Flags; use Flags; with Vhdl.Errors; use Vhdl.Errors; @@ -1421,7 +1422,7 @@ package body Simul.Execution is Unit := Get_Unit_Chain (Vhdl.Std_Package.Time_Type_Definition); while Unit /= Null_Iir loop exit when Vhdl.Evaluation.Get_Physical_Value (Unit) - = Iir_Int64 (Right.I64); + = Int64 (Right.I64); Unit := Get_Chain (Unit); end loop; if Unit = Null_Iir then @@ -2394,8 +2395,8 @@ package body Simul.Execution is when Iir_Value_I64 => null; when Iir_Value_F64 => - if Res.F64 > Ghdl_F64 (Iir_Int64'Last) or - Res.F64 < Ghdl_F64 (Iir_Int64'First) + if Res.F64 > Ghdl_F64 (Int64'Last) or + Res.F64 < Ghdl_F64 (Int64'First) then Error_Msg_Constraint (Loc); end if; @@ -3042,7 +3043,7 @@ package body Simul.Execution is when Iir_Kind_Integer_Literal => declare Lit_Type : constant Iir := Get_Base_Type (Get_Type (Expr)); - Lit : constant Iir_Int64 := Get_Value (Expr); + Lit : constant Int64 := Get_Value (Expr); begin case Get_Info (Lit_Type).Scalar_Mode is when Iir_Value_I64 => @@ -4378,11 +4379,11 @@ package body Simul.Execution is declare Choice_Type : constant Iir := Get_Type (Get_Choice_Expression (Assoc)); - Choice_Len : Iir_Int64; + Choice_Len : Int64; begin Choice_Len := Vhdl.Evaluation.Eval_Discrete_Type_Length (Get_String_Type_Bound_Type (Choice_Type)); - if Choice_Len /= Iir_Int64 (Value.Bounds.D (1).Length) then + if Choice_Len /= Int64 (Value.Bounds.D (1).Length) then Error_Msg_Constraint (Expr); end if; end; diff --git a/src/vhdl/simulate/simul-execution.ads b/src/vhdl/simulate/simul-execution.ads index ade4ac085..8df5ed882 100644 --- a/src/vhdl/simulate/simul-execution.ads +++ b/src/vhdl/simulate/simul-execution.ads @@ -16,7 +16,6 @@ -- Software Foundation, 59 Temple Place - Suite 330, Boston, MA -- 02111-1307, USA. -with Types; use Types; with Vhdl.Nodes; use Vhdl.Nodes; with Simul.Environments; use Simul.Environments; with Simul.Elaboration; use Simul.Elaboration; diff --git a/src/vhdl/simulate/simul-grt_interface.adb b/src/vhdl/simulate/simul-grt_interface.adb index 40069e908..e485d7d18 100644 --- a/src/vhdl/simulate/simul-grt_interface.adb +++ b/src/vhdl/simulate/simul-grt_interface.adb @@ -17,7 +17,6 @@ -- 02111-1307, USA. with Vhdl.Nodes; use Vhdl.Nodes; -with Types; use Types; package body Simul.Grt_Interface is To_Dir : constant array (Iir_Direction) of Ghdl_Dir_Type := diff --git a/src/vhdl/translate/trans-chap14.adb b/src/vhdl/translate/trans-chap14.adb index e95afb5c4..4618edcb1 100644 --- a/src/vhdl/translate/trans-chap14.adb +++ b/src/vhdl/translate/trans-chap14.adb @@ -577,7 +577,7 @@ package body Trans.Chap14 is Info : Type_Info_Acc; Var : O_Dnode; Data : Last_Time_Data; - Right_Bound : Iir_Int64; + Right_Bound : Int64; If_Blk : O_If_Block; begin Name := Chap6.Translate_Name (Prefix, Mode_Signal); diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb index 7d32e50f6..5cbf85e62 100644 --- a/src/vhdl/translate/trans-chap2.adb +++ b/src/vhdl/translate/trans-chap2.adb @@ -1455,7 +1455,7 @@ package body Trans.Chap2 is | Type_Iir_Constraint | Type_Iir_Mode | Type_Iir_Index32 - | Type_Iir_Int64 + | Type_Int64 | Type_Boolean | Type_Iir_Staticness | Type_Iir_All_Sensitized @@ -1467,7 +1467,7 @@ package body Trans.Chap2 is | Type_Iir_Direction | Type_Iir_Int32 | Type_Int32 - | Type_Iir_Fp64 + | Type_Fp64 | Type_Token_Type | Type_Name_Id => null; diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb index 971d52b31..8c3021d43 100644 --- a/src/vhdl/translate/trans-chap3.adb +++ b/src/vhdl/translate/trans-chap3.adb @@ -340,7 +340,7 @@ package body Trans.Chap3 is St : constant Iir := Get_Subtype_Definition (Get_Type_Declarator (Def)); L, H : Iir; - Lv, Hv : Iir_Int64; + Lv, Hv : Int64; begin Get_Low_High_Limit (Get_Range_Constraint (St), L, H); Lv := Get_Value (L); @@ -983,12 +983,12 @@ package body Trans.Chap3 is -- Get the length of DEF, ie the number of elements. -- If the length is not statically defined, returns -1. function Get_Array_Subtype_Length (Def : Iir_Array_Subtype_Definition) - return Iir_Int64 + return Int64 is Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Def); Index : Iir; - Idx_Len : Iir_Int64; - Len : Iir_Int64; + Idx_Len : Int64; + Len : Int64; begin -- Check if the bounds of the array are locally static. Len := 1; @@ -1059,7 +1059,7 @@ package body Trans.Chap3 is Info : constant Type_Info_Acc := Get_Info (Def); Pinfo : constant Type_Info_Acc := Get_Info (Parent_Type); - Len : Iir_Int64; + Len : Int64; Id : O_Ident; El_Constrained : Boolean; @@ -2068,24 +2068,24 @@ package body Trans.Chap3 is end; when Type_Mode_I64 => declare - V : Iir_Int64; + V : Int64; begin V := Get_Value (Lit); if Is_Hi then - return V = Iir_Int64'Last; + return V = Int64'Last; else - return V = Iir_Int64'First; + return V = Int64'First; end if; end; when Type_Mode_P64 => declare - V : Iir_Int64; + V : Int64; begin V := Get_Physical_Value (Lit); if Is_Hi then - return V = Iir_Int64'Last; + return V = Int64'Last; else - return V = Iir_Int64'First; + return V = Int64'First; end if; end; when Type_Mode_F64 => @@ -2657,7 +2657,7 @@ package body Trans.Chap3 is Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Atype); Nbr_Dim : constant Natural := Get_Nbr_Elements (Indexes_List); Index : Iir; - Val : Iir_Int64; + Val : Int64; Rng : Iir; begin Val := 1; diff --git a/src/vhdl/translate/trans-chap6.adb b/src/vhdl/translate/trans-chap6.adb index 9d0da87c8..a277d452b 100644 --- a/src/vhdl/translate/trans-chap6.adb +++ b/src/vhdl/translate/trans-chap6.adb @@ -310,8 +310,8 @@ package body Trans.Chap6 is Cond2 : O_Enode; Index : O_Enode; Index_Base_Type : Iir; - V : Iir_Int64; - B : Iir_Int64; + V : Int64; + B : Int64; begin B := Eval_Pos (Get_Left_Limit (Index_Range)); if Get_Expr_Staticness (Expr) = Locally then @@ -558,9 +558,9 @@ package body Trans.Chap6 is Slice_Index_Type : constant Iir := Get_Index_Type (Slice_Type, 0); Slice_Range : constant Iir := Get_Range_Constraint (Slice_Index_Type); - Prefix_Left, Slice_Left : Iir_Int64; - Off : Iir_Int64; - Slice_Length : Iir_Int64; + Prefix_Left, Slice_Left : Int64; + Off : Int64; + Slice_Length : Int64; begin Prefix_Left := Eval_Pos (Get_Left_Limit (Index_Range)); Slice_Left := Eval_Pos (Get_Left_Limit (Slice_Range)); diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 98cc8894e..9d1e0796c 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -199,7 +199,7 @@ package body Trans.Chap7 is Index_Type : constant Iir := Get_Index_Type (Aggr_Type, Dim - 1); Index_Range : constant Iir := Eval_Static_Range (Index_Type); - Len : constant Iir_Int64 := + Len : constant Int64 := Eval_Discrete_Range_Length (Index_Range); Assocs : constant Iir := Get_Association_Choices_Chain (Aggr); Vect : Iir_Array (0 .. Integer (Len - 1)); @@ -1229,7 +1229,7 @@ package body Trans.Chap7 is Expr_Type : constant Iir := Get_Return_Type (Concat_Imp); Index_Type : constant Iir := Get_Index_Type (Expr_Type, 0); Info : constant Type_Info_Acc := Get_Info (Expr_Type); - Static_Length : Iir_Int64 := 0; + Static_Length : Int64 := 0; Nbr_Dyn_Expr : Natural := 0; type Handle_Acc is access procedure (E : Iir); @@ -2971,7 +2971,7 @@ package body Trans.Chap7 is -- Assign EXPR to current position (defined by index VAR_INDEX), and -- update VAR_INDEX. Handles sub-aggregates. - procedure Do_Assign (Assoc : Iir; Expr : Iir; Assoc_Len : out Iir_Int64) + procedure Do_Assign (Assoc : Iir; Expr : Iir; Assoc_Len : out Int64) is Dest : Mnode; begin @@ -3008,7 +3008,7 @@ package body Trans.Chap7 is is P : Natural; El : Iir; - Assoc_Len : Iir_Int64; + Assoc_Len : Int64; begin -- First, assign positionnal association. -- FIXME: count the number of positionnal association and generate @@ -3072,7 +3072,7 @@ package body Trans.Chap7 is procedure Translate_Array_Aggregate_Gen_Named is El : Iir; - Assoc_Len : Iir_Int64; + Assoc_Len : Int64; begin El := Get_Association_Choices_Chain (Aggr); @@ -3525,7 +3525,7 @@ package body Trans.Chap7 is is Aggr_Type : constant Iir := Get_Type (Aggr); Assoc : Iir; - Static_Len : Iir_Int64; + Static_Len : Int64; Var_Len : O_Dnode; Expr_Type : Iir; Range_Type : Iir; @@ -4217,7 +4217,7 @@ package body Trans.Chap7 is declare Otype : constant O_Tnode := Get_Ortho_Type (Expr_Type, Mode_Value); - Val : Iir_Int64; + Val : Int64; begin -- Get the value now, as it may generate a constraint_error. Val := Get_Physical_Value (Expr); diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb index 79b05a055..427a30464 100644 --- a/src/vhdl/translate/trans-chap8.adb +++ b/src/vhdl/translate/trans-chap8.adb @@ -1206,7 +1206,7 @@ package body Trans.Chap8 is Expr : constant Iir := Get_Expression (Stmt); Expr_Type : Iir; Base_Type : Iir; - Sel_Length : Iir_Int64; + Sel_Length : Int64; Cond : O_Enode; begin -- Translate into if/elsif statements. @@ -1294,7 +1294,7 @@ package body Trans.Chap8 is -- Number of associations. Nbr_Assocs : Natural; - Sel_Length : Iir_Int64; + Sel_Length : Int64; -- Dichotomy table (table of choices). String_Type : O_Tnode; diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 58e0d6dcb..92ed100d5 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -1351,7 +1351,7 @@ package body Trans.Chap9 is | Type_Iir_Constraint | Type_Iir_Mode | Type_Iir_Index32 - | Type_Iir_Int64 + | Type_Int64 | Type_Boolean | Type_Iir_Staticness | Type_Iir_All_Sensitized @@ -1363,7 +1363,7 @@ package body Trans.Chap9 is | Type_Iir_Direction | Type_Iir_Int32 | Type_Int32 - | Type_Iir_Fp64 + | Type_Fp64 | Type_Token_Type | Type_Name_Id => null; diff --git a/src/vhdl/vhdl-disp_tree.adb b/src/vhdl/vhdl-disp_tree.adb index 02e750b16..c4953035d 100644 --- a/src/vhdl/vhdl-disp_tree.adb +++ b/src/vhdl/vhdl-disp_tree.adb @@ -530,8 +530,8 @@ package body Vhdl.Disp_Tree is Log_Line (Image_Iir_Mode (Get_Iir_Mode (N, F))); when Type_Iir_Index32 => Log_Line (Iir_Index32'Image (Get_Iir_Index32 (N, F))); - when Type_Iir_Int64 => - Log_Line (Iir_Int64'Image (Get_Iir_Int64 (N, F))); + when Type_Int64 => + Log_Line (Int64'Image (Get_Int64 (N, F))); when Type_Boolean => Log_Line (Image_Boolean (Get_Boolean (N, F))); @@ -566,8 +566,8 @@ package body Vhdl.Disp_Tree is Log_Line (Iir_Int32'Image (Get_Iir_Int32 (N, F))); when Type_Int32 => Log_Line (Int32'Image (Get_Int32 (N, F))); - when Type_Iir_Fp64 => - Log_Line (Iir_Fp64'Image (Get_Iir_Fp64 (N, F))); + when Type_Fp64 => + Log_Line (Fp64'Image (Get_Fp64 (N, F))); when Type_Time_Stamp_Id => Log_Line (Image_Time_Stamp_Id (Get_Time_Stamp_Id (N, F))); diff --git a/src/vhdl/vhdl-disp_vhdl.adb b/src/vhdl/vhdl-disp_vhdl.adb index f54d06788..e60480dfb 100644 --- a/src/vhdl/vhdl-disp_vhdl.adb +++ b/src/vhdl/vhdl-disp_vhdl.adb @@ -3582,9 +3582,9 @@ package body Vhdl.Disp_Vhdl is end case; end Disp_Vhdl; - procedure Disp_Int64 (Val: Iir_Int64) + procedure Disp_Int64 (Val: Int64) is - Str: constant String := Iir_Int64'Image (Val); + Str: constant String := Int64'Image (Val); begin if Str (Str'First) = ' ' then Put (Str (Str'First + 1 .. Str'Last)); @@ -3604,9 +3604,9 @@ package body Vhdl.Disp_Vhdl is end if; end Disp_Int32; - procedure Disp_Fp64 (Val: Iir_Fp64) + procedure Disp_Fp64 (Val: Fp64) is - Str: constant String := Iir_Fp64'Image (Val); + Str: constant String := Fp64'Image (Val); begin if Str (Str'First) = ' ' then Put (Str (Str'First + 1 .. Str'Last)); diff --git a/src/vhdl/vhdl-disp_vhdl.ads b/src/vhdl/vhdl-disp_vhdl.ads index b29a1e736..e69ab29f2 100644 --- a/src/vhdl/vhdl-disp_vhdl.ads +++ b/src/vhdl/vhdl-disp_vhdl.ads @@ -30,11 +30,11 @@ package Vhdl.Disp_Vhdl is -- Display an expression. -- Disp an iir_int64, without the leading blank. - procedure Disp_Int64 (Val: Iir_Int64); + procedure Disp_Int64 (Val: Int64); -- Disp an iir_int32, without the leading blank. procedure Disp_Int32 (Val: Iir_Int32); -- Disp an iir_Fp64, without the leading blank. - procedure Disp_Fp64 (Val: Iir_Fp64); + procedure Disp_Fp64 (Val: Fp64); end Vhdl.Disp_Vhdl; diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index ac38f006e..d6a8afd66 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -762,9 +762,9 @@ package body Vhdl.Errors is end case; end Disp_Name; - function Image (N : Iir_Int64) return String + function Image (N : Int64) return String is - Res : constant String := Iir_Int64'Image (N); + Res : constant String := Int64'Image (N); begin if Res (1) = ' ' then return Res (2 .. Res'Last); @@ -773,7 +773,7 @@ package body Vhdl.Errors is end if; end Image; - function Disp_Discrete (Dtype : Iir; Pos : Iir_Int64) return String is + function Disp_Discrete (Dtype : Iir; Pos : Int64) return String is begin case Get_Kind (Dtype) is when Iir_Kind_Integer_Type_Definition => diff --git a/src/vhdl/vhdl-errors.ads b/src/vhdl/vhdl-errors.ads index 5987a6782..b1b42c10c 100644 --- a/src/vhdl/vhdl-errors.ads +++ b/src/vhdl/vhdl-errors.ads @@ -114,7 +114,7 @@ package Vhdl.Errors is function Disp_Subprg (Subprg : Iir) return String; -- Print element POS of discrete type DTYPE. - function Disp_Discrete (Dtype : Iir; Pos : Iir_Int64) return String; + function Disp_Discrete (Dtype : Iir; Pos : Int64) return String; -- Disp the name of the type of NODE if known. -- Disp "unknown" if it is not known. diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index ae2a38bc4..71ee3b0d7 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -34,11 +34,11 @@ package body Vhdl.Evaluation is function Eval_Expr_Keep_Orig (Expr : Iir; Force : Boolean) return Iir; function Eval_Enum_To_String (Lit : Iir; Orig : Iir) return Iir; - function Eval_Integer_Image (Val : Iir_Int64; Orig : Iir) return Iir; + function Eval_Integer_Image (Val : Int64; Orig : Iir) return Iir; function Eval_Scalar_Compare (Left, Right : Iir) return Compare_Type; - function Get_Physical_Value (Expr : Iir) return Iir_Int64 + function Get_Physical_Value (Expr : Iir) return Int64 is pragma Unsuppress (Overflow_Check); Kind : constant Iir_Kind := Get_Kind (Expr); @@ -55,8 +55,7 @@ package body Vhdl.Evaluation is when Iir_Kind_Physical_Int_Literal => return Get_Value (Expr) * Get_Value (Unit); when Iir_Kind_Physical_Fp_Literal => - return Iir_Int64 - (Get_Fp_Value (Expr) * Iir_Fp64 (Get_Value (Unit))); + return Int64 (Get_Fp_Value (Expr) * Fp64 (Get_Value (Unit))); when others => raise Program_Error; end case; @@ -67,7 +66,7 @@ package body Vhdl.Evaluation is end case; end Get_Physical_Value; - function Build_Integer (Val : Iir_Int64; Origin : Iir) + function Build_Integer (Val : Int64; Origin : Iir) return Iir_Integer_Literal is Res : Iir_Integer_Literal; @@ -81,7 +80,7 @@ package body Vhdl.Evaluation is return Res; end Build_Integer; - function Build_Floating (Val : Iir_Fp64; Origin : Iir) + function Build_Floating (Val : Fp64; Origin : Iir) return Iir_Floating_Point_Literal is Res : Iir_Floating_Point_Literal; @@ -111,7 +110,7 @@ package body Vhdl.Evaluation is return Res; end Build_Enumeration_Constant; - function Build_Physical (Val : Iir_Int64; Origin : Iir) + function Build_Physical (Val : Int64; Origin : Iir) return Iir_Physical_Int_Literal is Res : Iir_Physical_Int_Literal; @@ -128,7 +127,7 @@ package body Vhdl.Evaluation is return Res; end Build_Physical; - function Build_Discrete (Val : Iir_Int64; Origin : Iir) return Iir is + function Build_Discrete (Val : Int64; Origin : Iir) return Iir is begin case Get_Kind (Get_Type (Origin)) is when Iir_Kind_Enumeration_Type_Definition @@ -309,9 +308,9 @@ package body Vhdl.Evaluation is case Get_Kind (Orig_Type) is when Iir_Kind_Integer_Type_Definition => if Is_Pos then - return Build_Integer (Iir_Int64'Last, Origin); + return Build_Integer (Int64'Last, Origin); else - return Build_Integer (Iir_Int64'First, Origin); + return Build_Integer (Int64'First, Origin); end if; when others => Error_Kind ("build_extreme_value", Orig_Type); @@ -322,12 +321,12 @@ package body Vhdl.Evaluation is -- left_limit and direction are set. -- Type of A_RANGE must have a range_constraint. -- Set the right limit of A_RANGE from LEN. - procedure Set_Right_Limit_By_Length (A_Range : Iir; Len : Iir_Int64) + procedure Set_Right_Limit_By_Length (A_Range : Iir; Len : Int64) is A_Type : constant Iir := Get_Type (A_Range); Left : constant Iir := Get_Left_Limit (A_Range); Right : Iir; - Pos : Iir_Int64; + Pos : Int64; begin pragma Assert (Get_Expr_Staticness (A_Range) = Locally); @@ -358,7 +357,7 @@ package body Vhdl.Evaluation is -- * the right bound -- The left bound *IS NOT* created, but points to the left bound of A_TYPE. function Create_Range_By_Length - (A_Type : Iir; Len : Iir_Int64; Loc : Location_Type) + (A_Type : Iir; Len : Int64; Loc : Location_Type) return Iir is Index_Constraint : Iir; @@ -405,7 +404,7 @@ package body Vhdl.Evaluation is -- Create a subtype of A_TYPE whose length is LEN. -- This is used to create subtypes for strings or aggregates. function Create_Range_Subtype_By_Length - (A_Type : Iir; Len : Iir_Int64; Loc : Location_Type) + (A_Type : Iir; Len : Int64; Loc : Location_Type) return Iir is Res : Iir; @@ -432,7 +431,7 @@ package body Vhdl.Evaluation is end Create_Unidim_Array_From_Index; function Create_Unidim_Array_By_Length - (Base_Type : Iir; Len : Iir_Int64; Loc : Iir) + (Base_Type : Iir; Len : Int64; Loc : Iir) return Iir_Array_Subtype_Definition is Index_Type : constant Iir := Get_Index_Type (Base_Type, 0); @@ -490,8 +489,8 @@ package body Vhdl.Evaluation is -- Assume no overflow. function Eval_Pos_In_Range (Rng : Iir; Expr : Iir) return Iir_Index32 is - Left_Pos : constant Iir_Int64 := Eval_Pos (Get_Left_Limit (Rng)); - Pos : constant Iir_Int64 := Eval_Pos (Expr); + Left_Pos : constant Int64 := Eval_Pos (Get_Left_Limit (Rng)); + Pos : constant Int64 := Eval_Pos (Expr); begin case Get_Direction (Rng) is when Iir_To => @@ -528,7 +527,7 @@ package body Vhdl.Evaluation is declare Rng : constant Iir := Get_Choice_Range (Assoc); Rng_Start : Iir; - Rng_Len : Iir_Int64; + Rng_Len : Int64; begin if Get_Direction (Rng) = Get_Direction (Choice_Range) then Rng_Start := Get_Left_Limit (Rng); @@ -564,7 +563,7 @@ package body Vhdl.Evaluation is Aggr_Type : constant Iir := Get_Type (Aggr); Index_Type : constant Iir := Get_Index_Type (Aggr_Type, 0); Index_Range : constant Iir := Eval_Static_Range (Index_Type); - Len : constant Iir_Int64 := Eval_Discrete_Range_Length (Index_Range); + Len : constant Int64 := Eval_Discrete_Range_Length (Index_Range); Assocs : constant Iir := Get_Association_Choices_Chain (Aggr); Vect : Iir_Array (0 .. Integer (Len - 1)); List : Iir_Flist; @@ -905,7 +904,7 @@ package body Vhdl.Evaluation is (Left, Right : Iir; Origin : Iir; Func : Iir_Predefined_Shift_Functions) return Iir is - Count : constant Iir_Int64 := Get_Value (Right); + Count : constant Int64 := Get_Value (Right); Arr_List : constant Iir_Flist := Get_Simple_Aggregate_List (Left); Len : constant Natural := Get_Nbr_Elements (Arr_List); Cnt : Natural; @@ -1118,7 +1117,7 @@ package body Vhdl.Evaluation is Set_Left_Limit (A_Range, Get_Left_Limit (Left_Range)); Set_Direction (A_Range, Get_Direction (Left_Range)); Location_Copy (A_Range, Orig); - Set_Right_Limit_By_Length (A_Range, Iir_Int64 (Res_Len)); + Set_Right_Limit_By_Length (A_Range, Int64 (Res_Len)); Index_Type := Create_Range_Subtype_From_Type (Left_Index, Get_Location (Orig)); Set_Range_Constraint (Index_Type, A_Range); @@ -1133,7 +1132,7 @@ package body Vhdl.Evaluation is -- concatenation is the direction of S, and the left bound of the -- result is S'LEFT. Res_Type := Create_Unidim_Array_By_Length - (Origin_Type, Iir_Int64 (Res_Len), Orig); + (Origin_Type, Int64 (Res_Len), Orig); end if; end if; -- FIXME: this is not necessarily a string, it may be an aggregate if @@ -1166,8 +1165,8 @@ package body Vhdl.Evaluation is end; when Iir_Kind_Physical_Type_Definition => declare - L_Val : constant Iir_Int64 := Get_Physical_Value (Left); - R_Val : constant Iir_Int64 := Get_Physical_Value (Right); + L_Val : constant Int64 := Get_Physical_Value (Left); + R_Val : constant Int64 := Get_Physical_Value (Right); begin if L_Val = R_Val then return Compare_Eq; @@ -1181,8 +1180,8 @@ package body Vhdl.Evaluation is end; when Iir_Kind_Integer_Type_Definition => declare - L_Val : constant Iir_Int64 := Get_Value (Left); - R_Val : constant Iir_Int64 := Get_Value (Right); + L_Val : constant Int64 := Get_Value (Left); + R_Val : constant Int64 := Get_Value (Right); begin if L_Val = R_Val then return Compare_Eq; @@ -1196,8 +1195,8 @@ package body Vhdl.Evaluation is end; when Iir_Kind_Floating_Type_Definition => declare - L_Val : constant Iir_Fp64 := Get_Fp_Value (Left); - R_Val : constant Iir_Fp64 := Get_Fp_Value (Right); + L_Val : constant Fp64 := Get_Fp_Value (Left); + R_Val : constant Fp64 := Get_Fp_Value (Right); begin if L_Val = R_Val then return Compare_Eq; @@ -1395,9 +1394,9 @@ package body Vhdl.Evaluation is end if; when Iir_Predefined_Floating_Exp => declare - Exp : Iir_Int64; - Res : Iir_Fp64; - Val : Iir_Fp64; + Exp : Int64; + Res : Fp64; + Val : Fp64; begin Res := 1.0; Val := Get_Fp_Value (Left); @@ -1478,25 +1477,25 @@ package body Vhdl.Evaluation is when Iir_Predefined_Real_Physical_Mul => -- FIXME: overflow?? return Build_Physical - (Iir_Int64 (Get_Fp_Value (Left) - * Iir_Fp64 (Get_Physical_Value (Right))), Orig); + (Int64 (Get_Fp_Value (Left) + * Fp64 (Get_Physical_Value (Right))), Orig); when Iir_Predefined_Physical_Real_Mul => -- FIXME: overflow?? return Build_Physical - (Iir_Int64 (Iir_Fp64 (Get_Physical_Value (Left)) + (Int64 (Fp64 (Get_Physical_Value (Left)) * Get_Fp_Value (Right)), Orig); when Iir_Predefined_Physical_Real_Div => -- FIXME: overflow?? return Build_Physical - (Iir_Int64 (Iir_Fp64 (Get_Physical_Value (Left)) + (Int64 (Fp64 (Get_Physical_Value (Left)) / Get_Fp_Value (Right)), Orig); when Iir_Predefined_Physical_Minimum => - return Build_Physical (Iir_Int64'Min (Get_Physical_Value (Left), + return Build_Physical (Int64'Min (Get_Physical_Value (Left), Get_Physical_Value (Right)), Orig); when Iir_Predefined_Physical_Maximum => - return Build_Physical (Iir_Int64'Max (Get_Physical_Value (Left), + return Build_Physical (Int64'Max (Get_Physical_Value (Left), Get_Physical_Value (Right)), Orig); @@ -1578,13 +1577,13 @@ package body Vhdl.Evaluation is when Iir_Predefined_Universal_R_I_Mul => return Build_Floating - (Get_Fp_Value (Left) * Iir_Fp64 (Get_Value (Right)), Orig); + (Get_Fp_Value (Left) * Fp64 (Get_Value (Right)), Orig); when Iir_Predefined_Universal_I_R_Mul => return Build_Floating - (Iir_Fp64 (Get_Value (Left)) * Get_Fp_Value (Right), Orig); + (Fp64 (Get_Value (Left)) * Get_Fp_Value (Right), Orig); when Iir_Predefined_Universal_R_I_Div => return Build_Floating - (Get_Fp_Value (Left) / Iir_Fp64 (Get_Value (Right)), Orig); + (Get_Fp_Value (Left) / Fp64 (Get_Value (Right)), Orig); when Iir_Predefined_Array_Sll | Iir_Predefined_Array_Srl @@ -1777,12 +1776,12 @@ package body Vhdl.Evaluation is return Get_Nth_Element (Get_Index_Subtype_List (Prefix_Type), Dim - 1); end Eval_Array_Attribute; - function Eval_Integer_Image (Val : Iir_Int64; Orig : Iir) return Iir + function Eval_Integer_Image (Val : Int64; Orig : Iir) return Iir is use Str_Table; Img : String (1 .. 24); -- 23 is enough, 24 is rounded. L : Natural; - V : Iir_Int64; + V : Int64; Id : String8_Id; begin V := Val; @@ -1804,7 +1803,7 @@ package body Vhdl.Evaluation is return Build_String (Id, Nat32 (Img'Last - L), Orig); end Eval_Integer_Image; - function Eval_Floating_Image (Val : Iir_Fp64; Orig : Iir) return Iir + function Eval_Floating_Image (Val : Fp64; Orig : Iir) return Iir is use Str_Table; Id : String8_Id; @@ -1827,7 +1826,7 @@ package body Vhdl.Evaluation is Res := Build_String (Id, Int32 (P), Orig); -- FIXME: this is not correct since the type is *not* constrained. Set_Type (Res, Create_Unidim_Array_By_Length - (Get_Type (Orig), Iir_Int64 (P), Orig)); + (Get_Type (Orig), Int64 (P), Orig)); return Res; end Eval_Floating_Image; @@ -1872,7 +1871,7 @@ package body Vhdl.Evaluation is function Eval_Physical_Image (Phys, Expr: Iir) return Iir is -- Reduces to the base unit (e.g. femtoseconds). - Value : constant String := Iir_Int64'Image (Get_Physical_Value (Phys)); + Value : constant String := Int64'Image (Get_Physical_Value (Phys)); Unit : constant Iir := Get_Primary_Unit (Get_Base_Type (Get_Type (Phys))); UnitName : constant String := Image_Identifier (Unit); @@ -1898,7 +1897,7 @@ package body Vhdl.Evaluation is function Build_Physical_Value (Val: String; Phys_Type, Expr: Iir) return Iir is UnitName : String (Val'range); - Mult : Iir_Int64; + Mult : Int64; Sep : Natural; Found_Unit : Boolean := false; Found_Real : Boolean := false; @@ -1939,12 +1938,12 @@ package body Vhdl.Evaluation is Mult := Get_Value (Get_Physical_Literal (Unit)); if Found_Real then return Build_Physical - (Iir_Int64 (Iir_Fp64'Value (Val (Val'First .. Sep)) - * Iir_Fp64 (Mult)), + (Int64 (Fp64'Value (Val (Val'First .. Sep)) + * Fp64 (Mult)), Expr); else return Build_Physical - (Iir_Int64'Value (Val (Val'First .. Sep)) * Mult, Expr); + (Int64'Value (Val (Val'First .. Sep)) * Mult, Expr); end if; end Build_Physical_Value; @@ -2002,17 +2001,17 @@ package body Vhdl.Evaluation is return Build_String (Image_Id, Nat32 (Len), Orig); end Eval_Enum_To_String; - function Eval_Incdec (Expr : Iir; N : Iir_Int64; Origin : Iir) return Iir + function Eval_Incdec (Expr : Iir; N : Int64; Origin : Iir) return Iir is - P : Iir_Int64; + P : Int64; begin case Get_Kind (Expr) is when Iir_Kind_Integer_Literal => return Build_Integer (Get_Value (Expr) + N, Origin); when Iir_Kind_Enumeration_Literal => - P := Iir_Int64 (Get_Enum_Pos (Expr)) + N; + P := Int64 (Get_Enum_Pos (Expr)) + N; if P < 0 - or else (P >= Iir_Int64 + or else (P >= Int64 (Get_Nbr_Elements (Get_Enumeration_Literal_List (Get_Base_Type (Get_Type (Expr)))))) @@ -2130,14 +2129,14 @@ package body Vhdl.Evaluation is Res := Build_Integer (Get_Value (Val), Conv); when Iir_Kind_Floating_Type_Definition => Res := Build_Integer - (Iir_Int64 (Get_Fp_Value (Val)), Conv); + (Int64 (Get_Fp_Value (Val)), Conv); when others => Error_Kind ("eval_type_conversion(1)", Val_Type); end case; when Iir_Kind_Floating_Type_Definition => case Get_Kind (Val_Type) is when Iir_Kind_Integer_Type_Definition => - Res := Build_Floating (Iir_Fp64 (Get_Value (Val)), Conv); + Res := Build_Floating (Fp64 (Get_Value (Val)), Conv); when Iir_Kind_Floating_Type_Definition => Res := Build_Floating (Get_Fp_Value (Val), Conv); when others => @@ -2207,11 +2206,11 @@ package body Vhdl.Evaluation is begin case Get_Kind (Base_Type) is when Iir_Kind_Integer_Type_Definition => - return Build_Discrete (Iir_Int64'Value (Value1), Orig); + return Build_Discrete (Int64'Value (Value1), Orig); when Iir_Kind_Enumeration_Type_Definition => return Build_Enumeration_Value (Value1, Base_Type, Orig); when Iir_Kind_Floating_Type_Definition => - return Build_Floating (Iir_Fp64'value (Value1), Orig); + return Build_Floating (Fp64'value (Value1), Orig); when Iir_Kind_Physical_Type_Definition => return Build_Physical_Value (Value1, Base_Type, Orig); when others => @@ -2310,7 +2309,7 @@ package body Vhdl.Evaluation is Assoc_Expr : Iir; Aggr_Bounds : Iir; Aggr : Iir; - Cur_Pos : Iir_Int64; + Cur_Pos : Int64; Res : Iir; begin Aggr := Prefix; @@ -2458,8 +2457,8 @@ package body Vhdl.Evaluation is Aggr_Bounds : Iir; Cur_Off : Iir_Index32; Res : Iir; - Left_Pos : Iir_Int64; - Assoc_Pos : Iir_Int64; + Left_Pos : Int64; + Assoc_Pos : Int64; begin Aggr_Bounds := Eval_Static_Range (Get_Nth_Element (Indexes_Type, Dim)); Left_Pos := Eval_Pos (Eval_Discrete_Range_Left (Aggr_Bounds)); @@ -2502,9 +2501,9 @@ package body Vhdl.Evaluation is when Iir_Kind_Choice_By_Range => declare Rng : Iir; - Left : Iir_Int64; - Right : Iir_Int64; - Hi, Lo : Iir_Int64; + Left : Int64; + Right : Int64; + Hi, Lo : Int64; Lo_Off, Hi_Off : Iir_Index32; begin Rng := Eval_Range (Get_Choice_Range (Assoc)); @@ -2688,7 +2687,7 @@ package body Vhdl.Evaluation is declare Expr_Type : constant Iir := Get_Type (Expr); Val_Expr : Iir; - Val : Iir_Int64; + Val : Int64; begin Val_Expr := Eval_Static_Expr (Get_Parameter (Expr)); Val := Eval_Pos (Val_Expr); @@ -2835,7 +2834,7 @@ package body Vhdl.Evaluation is | Iir_Kind_Rightof_Attribute => declare Rng : Iir; - N : Iir_Int64; + N : Int64; Prefix_Type : constant Iir := Get_Type (Get_Prefix (Expr)); Res : Iir; begin @@ -2949,7 +2948,7 @@ package body Vhdl.Evaluation is is Expr_Type : constant Iir := Get_Type (Expr); Indexes : Iir_Flist; - Len : Iir_Int64; + Len : Int64; begin -- Consider only arrays. Records are never composite. if Get_Kind (Expr_Type) /= Iir_Kind_Array_Subtype_Definition then @@ -3128,7 +3127,7 @@ package body Vhdl.Evaluation is end if; end Eval_Expr_Check_If_Static; - function Eval_Int_In_Range (Val : Iir_Int64; Bound : Iir) return Boolean is + function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean is begin case Get_Kind (Bound) is when Iir_Kind_Range_Expression => @@ -3152,9 +3151,9 @@ package body Vhdl.Evaluation is return True; end Eval_Int_In_Range; - function Eval_Phys_In_Range (Val : Iir_Int64; Bound : Iir) return Boolean + function Eval_Phys_In_Range (Val : Int64; Bound : Iir) return Boolean is - Left, Right : Iir_Int64; + Left, Right : Int64; begin case Get_Kind (Bound) is when Iir_Kind_Range_Expression => @@ -3186,7 +3185,7 @@ package body Vhdl.Evaluation is return True; end Eval_Phys_In_Range; - function Eval_Fp_In_Range (Val : Iir_Fp64; Bound : Iir) return Boolean is + function Eval_Fp_In_Range (Val : Fp64; Bound : Iir) return Boolean is begin case Get_Kind (Bound) is when Iir_Kind_Range_Expression => @@ -3267,7 +3266,7 @@ package body Vhdl.Evaluation is -- 'val attribute. Type_Range := Get_Range_Constraint (Sub_Type); return Eval_Int_In_Range - (Iir_Int64 (Get_Enum_Pos (Val)), Type_Range); + (Int64 (Get_Enum_Pos (Val)), Type_Range); when Iir_Kind_Physical_Subtype_Definition => if Get_Expr_Staticness (Val) /= Locally @@ -3390,7 +3389,7 @@ package body Vhdl.Evaluation is | Iir_Kind_Enumeration_Subtype_Definition | Iir_Kind_Enumeration_Type_Definition => declare - L, R : Iir_Int64; + L, R : Int64; begin -- Check for null range. L := Eval_Pos (Get_Left_Limit (Range_Constraint)); @@ -3410,7 +3409,7 @@ package body Vhdl.Evaluation is end; when Iir_Kind_Floating_Subtype_Definition => declare - L, R : Iir_Fp64; + L, R : Fp64; begin -- Check for null range. L := Get_Fp_Value (Get_Left_Limit (Range_Constraint)); @@ -3446,12 +3445,12 @@ package body Vhdl.Evaluation is end if; end Eval_Check_Range; - function Eval_Discrete_Range_Length (Constraint : Iir) return Iir_Int64 + function Eval_Discrete_Range_Length (Constraint : Iir) return Int64 is -- We don't want to deal with very large ranges here. pragma Suppress (Overflow_Check); - Res : Iir_Int64; - Left, Right : Iir_Int64; + Res : Int64; + Left, Right : Int64; begin Left := Eval_Pos (Get_Left_Limit (Constraint)); Right := Eval_Pos (Get_Right_Limit (Constraint)); @@ -3474,7 +3473,7 @@ package body Vhdl.Evaluation is return Res; end Eval_Discrete_Range_Length; - function Eval_Discrete_Type_Length (Sub_Type : Iir) return Iir_Int64 + function Eval_Discrete_Type_Length (Sub_Type : Iir) return Int64 is begin case Get_Kind (Sub_Type) is @@ -3490,7 +3489,7 @@ package body Vhdl.Evaluation is function Eval_Is_Null_Discrete_Range (Rng : Iir) return Boolean is - Left, Right : Iir_Int64; + Left, Right : Int64; begin Left := Eval_Pos (Get_Left_Limit (Rng)); Right := Eval_Pos (Get_Right_Limit (Rng)); @@ -3502,13 +3501,13 @@ package body Vhdl.Evaluation is end case; end Eval_Is_Null_Discrete_Range; - function Eval_Pos (Expr : Iir) return Iir_Int64 is + function Eval_Pos (Expr : Iir) return Int64 is begin case Get_Kind (Expr) is when Iir_Kind_Integer_Literal => return Get_Value (Expr); when Iir_Kind_Enumeration_Literal => - return Iir_Int64 (Get_Enum_Pos (Expr)); + return Int64 (Get_Enum_Pos (Expr)); when Iir_Kind_Physical_Int_Literal | Iir_Kind_Physical_Fp_Literal | Iir_Kind_Unit_Declaration => diff --git a/src/vhdl/vhdl-evaluation.ads b/src/vhdl/vhdl-evaluation.ads index 6d913a4d2..48a36a886 100644 --- a/src/vhdl/vhdl-evaluation.ads +++ b/src/vhdl/vhdl-evaluation.ads @@ -43,7 +43,7 @@ package Vhdl.Evaluation is -- Get the value of a physical integer literal or unit. May propagate -- Constraint_Error. - function Get_Physical_Value (Expr : Iir) return Iir_Int64; + function Get_Physical_Value (Expr : Iir) return Int64; -- Get the parameter of an attribute, or 1 if doesn't exist. function Eval_Attribute_Parameter_Or_1 (Attr : Iir) return Natural; @@ -115,13 +115,13 @@ package Vhdl.Evaluation is return Boolean; -- Return TRUE iff VAL belongs to BOUND. - function Eval_Int_In_Range (Val : Iir_Int64; Bound : Iir) return Boolean; + function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean; -- Return the length of the discrete range CONSTRAINT. - function Eval_Discrete_Range_Length (Constraint : Iir) return Iir_Int64; + function Eval_Discrete_Range_Length (Constraint : Iir) return Int64; -- Return the length of SUB_TYPE. - function Eval_Discrete_Type_Length (Sub_Type : Iir) return Iir_Int64; + function Eval_Discrete_Type_Length (Sub_Type : Iir) return Int64; -- Get the left bound of a range constraint. -- Note: the range constraint may be an attribute or a subtype. @@ -133,7 +133,7 @@ package Vhdl.Evaluation is -- Return the position of EXPR, ie the result of sub_type'pos (EXPR), where -- sub_type is the type of expr. -- EXPR must be of a discrete subtype. - function Eval_Pos (Expr : Iir) return Iir_Int64; + function Eval_Pos (Expr : Iir) return Int64; -- Return True iff L and R (scalar literals) are equal. function Eval_Is_Eq (L, R : Iir) return Boolean; @@ -155,13 +155,13 @@ package Vhdl.Evaluation is -- Create an array subtype from LEN and BASE_TYPE, according to rules -- of LRM93 7.3.2.2. (which are the same as LRM93 7.2.4). function Create_Unidim_Array_By_Length - (Base_Type : Iir; Len : Iir_Int64; Loc : Iir) + (Base_Type : Iir; Len : Int64; Loc : Iir) return Iir_Array_Subtype_Definition; -- Create a subtype of A_TYPE whose length is LEN. -- This is used to create subtypes for strings or aggregates. function Create_Range_Subtype_By_Length - (A_Type : Iir; Len : Iir_Int64; Loc : Location_Type) + (A_Type : Iir; Len : Int64; Loc : Location_Type) return Iir; -- Compute ATYPE'value (VALUE) using origin ORIG, but without checking diff --git a/src/vhdl/vhdl-ieee-vital_timing.adb b/src/vhdl/vhdl-ieee-vital_timing.adb index af68caabc..89cfc7df0 100644 --- a/src/vhdl/vhdl-ieee-vital_timing.adb +++ b/src/vhdl/vhdl-ieee-vital_timing.adb @@ -553,10 +553,10 @@ package body Vhdl.Ieee.Vital_Timing is -- If P is a scalar port, return PORT_LENGTH_SCALAR -- If P is a vector, return the length of the vector (>= 0) -- Otherwise, return PORT_LENGTH_ERROR. - Port_Length_Unknown : constant Iir_Int64 := -1; - Port_Length_Scalar : constant Iir_Int64 := -2; - Port_Length_Error : constant Iir_Int64 := -3; - function Get_Port_Length (P : Iir) return Iir_Int64 + Port_Length_Unknown : constant Int64 := -1; + Port_Length_Scalar : constant Int64 := -2; + Port_Length_Error : constant Int64 := -3; + function Get_Port_Length (P : Iir) return Int64 is Ptype : constant Iir := Get_Type (P); Itype : Iir; @@ -631,7 +631,7 @@ package body Vhdl.Ieee.Vital_Timing is return Timing_Type_Bad; end Get_Timing_Generic_Type_Kind; - function Get_Timing_Generic_Type_Length return Iir_Int64 + function Get_Timing_Generic_Type_Length return Int64 is Itype : Iir; begin @@ -657,8 +657,8 @@ package body Vhdl.Ieee.Vital_Timing is Is_Scalar : Boolean := False) is Kind : Timing_Generic_Type_Kind; - Len : Iir_Int64; - Len1 : Iir_Int64; + Len : Int64; + Len1 : Int64; begin Kind := Get_Timing_Generic_Type_Kind; if P = Null_Iir or Kind = Timing_Type_Bad then @@ -722,9 +722,9 @@ package body Vhdl.Ieee.Vital_Timing is Is_Scalar : Boolean := False) is Kind : Timing_Generic_Type_Kind; - Len1 : Iir_Int64; - Len2 : Iir_Int64; - Lenp : Iir_Int64; + Len1 : Int64; + Len2 : Int64; + Lenp : Int64; begin Kind := Get_Timing_Generic_Type_Kind; if P1 = Null_Iir or P2 = Null_Iir or Kind = Timing_Type_Bad then diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 007209b23..71f1eb722 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1616,37 +1616,37 @@ package body Vhdl.Nodes is Set_Field12 (Design_Unit, Int32_To_Iir (Line)); end Set_Design_Unit_Source_Col; - type Iir_Int64_Conv is record + type Int64_Conv is record Field4: Iir; Field5: Iir; end record; - pragma Pack (Iir_Int64_Conv); - pragma Assert (Iir_Int64_Conv'Size = Iir_Int64'Size); + pragma Pack (Int64_Conv); + pragma Assert (Int64_Conv'Size = Int64'Size); - function Get_Value (Lit : Iir) return Iir_Int64 + function Get_Value (Lit : Iir) return Int64 is - function To_Iir_Int64 is new Ada.Unchecked_Conversion - (Iir_Int64_Conv, Iir_Int64); - Conv : Iir_Int64_Conv; + function To_Int64 is new Ada.Unchecked_Conversion + (Int64_Conv, Int64); + Conv : Int64_Conv; begin pragma Assert (Lit /= Null_Iir); pragma Assert (Has_Value (Get_Kind (Lit)), "no field Value"); Conv.Field4 := Get_Field4 (Lit); Conv.Field5 := Get_Field5 (Lit); - return To_Iir_Int64 (Conv); + return To_Int64 (Conv); end Get_Value; - procedure Set_Value (Lit : Iir; Val : Iir_Int64) + procedure Set_Value (Lit : Iir; Val : Int64) is - function To_Iir_Int64_Conv is new Ada.Unchecked_Conversion - (Iir_Int64, Iir_Int64_Conv); - Conv : Iir_Int64_Conv; + function To_Int64_Conv is new Ada.Unchecked_Conversion + (Int64, Int64_Conv); + Conv : Int64_Conv; begin pragma Assert (Lit /= Null_Iir); pragma Assert (Has_Value (Get_Kind (Lit)), "no field Value"); - Conv := To_Iir_Int64_Conv (Val); + Conv := To_Int64_Conv (Val); Set_Field4 (Lit, Conv.Field4); Set_Field5 (Lit, Conv.Field5); end Set_Value; @@ -1683,37 +1683,37 @@ package body Vhdl.Nodes is Set_Field4 (Unit, Lit); end Set_Physical_Literal; - type Iir_Fp64_Conv is record + type Fp64_Conv is record Field4: Iir; Field5: Iir; end record; - pragma Pack (Iir_Fp64_Conv); - pragma Assert (Iir_Fp64_Conv'Size = Iir_Fp64'Size); + pragma Pack (Fp64_Conv); + pragma Assert (Fp64_Conv'Size = Fp64'Size); - function Get_Fp_Value (Lit : Iir) return Iir_Fp64 + function Get_Fp_Value (Lit : Iir) return Fp64 is - function To_Iir_Fp64 is new Ada.Unchecked_Conversion - (Iir_Fp64_Conv, Iir_Fp64); - Conv : Iir_Fp64_Conv; + function To_Fp64 is new Ada.Unchecked_Conversion + (Fp64_Conv, Fp64); + Conv : Fp64_Conv; begin pragma Assert (Lit /= Null_Iir); pragma Assert (Has_Fp_Value (Get_Kind (Lit)), "no field Fp_Value"); Conv.Field4 := Get_Field4 (Lit); Conv.Field5 := Get_Field5 (Lit); - return To_Iir_Fp64 (Conv); + return To_Fp64 (Conv); end Get_Fp_Value; - procedure Set_Fp_Value (Lit : Iir; Val : Iir_Fp64) + procedure Set_Fp_Value (Lit : Iir; Val : Fp64) is - function To_Iir_Fp64_Conv is new Ada.Unchecked_Conversion - (Iir_Fp64, Iir_Fp64_Conv); - Conv : Iir_Fp64_Conv; + function To_Fp64_Conv is new Ada.Unchecked_Conversion + (Fp64, Fp64_Conv); + Conv : Fp64_Conv; begin pragma Assert (Lit /= Null_Iir); pragma Assert (Has_Fp_Value (Get_Kind (Lit)), "no field Fp_Value"); - Conv := To_Iir_Fp64_Conv (Val); + Conv := To_Fp64_Conv (Val); Set_Field4 (Lit, Conv.Field4); Set_Field5 (Lit, Conv.Field5); end Set_Fp_Value; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 261633812..4fc779c6b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4945,6 +4945,12 @@ package Vhdl.Nodes is Procedure_Parameter_Interface_List .. Function_Parameter_Interface_List; + -- iir_int32 is aimed at containing integer literal values. + type Iir_Int32 is new Int32; + + -- iir_index32 is aimed at containing an array index. + type Iir_Index32 is new Nat32; + --------------- -- subranges -- --------------- @@ -6007,8 +6013,8 @@ package Vhdl.Nodes is -- Value of an integer/physical literal. -- Field: Field4,Field5 (grp) - function Get_Value (Lit : Iir) return Iir_Int64; - procedure Set_Value (Lit : Iir; Val : Iir_Int64); + function Get_Value (Lit : Iir) return Int64; + procedure Set_Value (Lit : Iir; Val : Int64); -- Position (same as lit_type'pos) of an enumeration literal. -- Field: Field5 (pos) @@ -6021,8 +6027,8 @@ package Vhdl.Nodes is -- Value of a floating point literal. -- Field: Field4,Field5 (grp) - function Get_Fp_Value (Lit : Iir) return Iir_Fp64; - procedure Set_Fp_Value (Lit : Iir; Val : Iir_Fp64); + function Get_Fp_Value (Lit : Iir) return Fp64; + procedure Set_Fp_Value (Lit : Iir; Val : Fp64); -- List of elements of a simple aggregate. -- Field: Field4 Ref (uc) diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index f2752d528..f7486e875 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -43,10 +43,10 @@ package body Vhdl.Nodes_Meta is Field_Design_Unit_Source_Pos => Type_Source_Ptr, Field_Design_Unit_Source_Line => Type_Int32, Field_Design_Unit_Source_Col => Type_Int32, - Field_Value => Type_Iir_Int64, + Field_Value => Type_Int64, Field_Enum_Pos => Type_Iir_Int32, Field_Physical_Literal => Type_Iir, - Field_Fp_Value => Type_Iir_Fp64, + Field_Fp_Value => Type_Fp64, Field_Simple_Aggregate_List => Type_Iir_Flist, Field_String8_Id => Type_String8_Id, Field_String_Length => Type_Int32, @@ -5060,6 +5060,30 @@ package body Vhdl.Nodes_Meta is end case; end Set_File_Checksum_Id; + function Get_Fp64 + (N : Iir; F : Fields_Enum) return Fp64 is + begin + pragma Assert (Fields_Type (F) = Type_Fp64); + case F is + when Field_Fp_Value => + return Get_Fp_Value (N); + when others => + raise Internal_Error; + end case; + end Get_Fp64; + + procedure Set_Fp64 + (N : Iir; F : Fields_Enum; V: Fp64) is + begin + pragma Assert (Fields_Type (F) = Type_Fp64); + case F is + when Field_Fp_Value => + Set_Fp_Value (N, V); + when others => + raise Internal_Error; + end case; + end Set_Fp64; + function Get_Iir (N : Iir; F : Fields_Enum) return Iir is begin @@ -6016,30 +6040,6 @@ package body Vhdl.Nodes_Meta is end case; end Set_Iir_Flist; - function Get_Iir_Fp64 - (N : Iir; F : Fields_Enum) return Iir_Fp64 is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Fp64); - case F is - when Field_Fp_Value => - return Get_Fp_Value (N); - when others => - raise Internal_Error; - end case; - end Get_Iir_Fp64; - - procedure Set_Iir_Fp64 - (N : Iir; F : Fields_Enum; V: Iir_Fp64) is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Fp64); - case F is - when Field_Fp_Value => - Set_Fp_Value (N, V); - when others => - raise Internal_Error; - end case; - end Set_Iir_Fp64; - function Get_Iir_Index32 (N : Iir; F : Fields_Enum) return Iir_Index32 is begin @@ -6108,30 +6108,6 @@ package body Vhdl.Nodes_Meta is end case; end Set_Iir_Int32; - function Get_Iir_Int64 - (N : Iir; F : Fields_Enum) return Iir_Int64 is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Int64); - case F is - when Field_Value => - return Get_Value (N); - when others => - raise Internal_Error; - end case; - end Get_Iir_Int64; - - procedure Set_Iir_Int64 - (N : Iir; F : Fields_Enum; V: Iir_Int64) is - begin - pragma Assert (Fields_Type (F) = Type_Iir_Int64); - case F is - when Field_Value => - Set_Value (N, V); - when others => - raise Internal_Error; - end case; - end Set_Iir_Int64; - function Get_Iir_List (N : Iir; F : Fields_Enum) return Iir_List is begin @@ -6356,6 +6332,30 @@ package body Vhdl.Nodes_Meta is end case; end Set_Int32; + function Get_Int64 + (N : Iir; F : Fields_Enum) return Int64 is + begin + pragma Assert (Fields_Type (F) = Type_Int64); + case F is + when Field_Value => + return Get_Value (N); + when others => + raise Internal_Error; + end case; + end Get_Int64; + + procedure Set_Int64 + (N : Iir; F : Fields_Enum; V: Int64) is + begin + pragma Assert (Fields_Type (F) = Type_Int64); + case F is + when Field_Value => + Set_Value (N, V); + when others => + raise Internal_Error; + end case; + end Set_Int64; + function Get_Name_Id (N : Iir; F : Fields_Enum) return Name_Id is begin diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads index 38113509f..02f86439e 100644 --- a/src/vhdl/vhdl-nodes_meta.ads +++ b/src/vhdl/vhdl-nodes_meta.ads @@ -28,16 +28,15 @@ package Vhdl.Nodes_Meta is Type_Date_State_Type, Type_Date_Type, Type_File_Checksum_Id, + Type_Fp64, Type_Iir, Type_Iir_All_Sensitized, Type_Iir_Constraint, Type_Iir_Delay_Mechanism, Type_Iir_Direction, Type_Iir_Flist, - Type_Iir_Fp64, Type_Iir_Index32, Type_Iir_Int32, - Type_Iir_Int64, Type_Iir_List, Type_Iir_Mode, Type_Iir_Predefined_Functions, @@ -45,6 +44,7 @@ package Vhdl.Nodes_Meta is Type_Iir_Signal_Kind, Type_Iir_Staticness, Type_Int32, + Type_Int64, Type_Name_Id, Type_Number_Base_Type, Type_PSL_NFA, @@ -453,6 +453,11 @@ package Vhdl.Nodes_Meta is procedure Set_File_Checksum_Id (N : Iir; F : Fields_Enum; V: File_Checksum_Id); + function Get_Fp64 + (N : Iir; F : Fields_Enum) return Fp64; + procedure Set_Fp64 + (N : Iir; F : Fields_Enum; V: Fp64); + function Get_Iir (N : Iir; F : Fields_Enum) return Iir; procedure Set_Iir @@ -483,11 +488,6 @@ package Vhdl.Nodes_Meta is procedure Set_Iir_Flist (N : Iir; F : Fields_Enum; V: Iir_Flist); - function Get_Iir_Fp64 - (N : Iir; F : Fields_Enum) return Iir_Fp64; - procedure Set_Iir_Fp64 - (N : Iir; F : Fields_Enum; V: Iir_Fp64); - function Get_Iir_Index32 (N : Iir; F : Fields_Enum) return Iir_Index32; procedure Set_Iir_Index32 @@ -498,11 +498,6 @@ package Vhdl.Nodes_Meta is procedure Set_Iir_Int32 (N : Iir; F : Fields_Enum; V: Iir_Int32); - function Get_Iir_Int64 - (N : Iir; F : Fields_Enum) return Iir_Int64; - procedure Set_Iir_Int64 - (N : Iir; F : Fields_Enum; V: Iir_Int64); - function Get_Iir_List (N : Iir; F : Fields_Enum) return Iir_List; procedure Set_Iir_List @@ -538,6 +533,11 @@ package Vhdl.Nodes_Meta is procedure Set_Int32 (N : Iir; F : Fields_Enum; V: Int32); + function Get_Int64 + (N : Iir; F : Fields_Enum) return Int64; + procedure Set_Int64 + (N : Iir; F : Fields_Enum; V: Int64); + function Get_Name_Id (N : Iir; F : Fields_Enum) return Name_Id; procedure Set_Name_Id diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 63c67ec29..d21fd97ff 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -5461,7 +5461,7 @@ package body Vhdl.Parse is -- postcond: likewise -- -- Return an integer_literal or a physical_literal. - function Parse_Integer_Literal (Val : Iir_Int64) return Iir + function Parse_Integer_Literal (Val : Int64) return Iir is Res : Iir; begin @@ -5509,8 +5509,8 @@ package body Vhdl.Parse is function Parse_Primary return Iir_Expression is Res: Iir_Expression; - Int: Iir_Int64; - Fp: Iir_Fp64; + Int: Int64; + Fp: Fp64; Loc: Location_Type; begin case Current_Token is diff --git a/src/vhdl/vhdl-scanner-scan_literal.adb b/src/vhdl/vhdl-scanner-scan_literal.adb index 9006587fc..b13f328e8 100644 --- a/src/vhdl/vhdl-scanner-scan_literal.adb +++ b/src/vhdl/vhdl-scanner-scan_literal.adb @@ -106,7 +106,7 @@ begin -- a universal integer. Current_Token := Tok_Integer; -- No possible overflow. - Current_Context.Int64 := Iir_Int64 (D); + Current_Context.Lit_Int64 := Int64 (D); return; elsif D >= (Natural'Last / 10) - 1 then -- Number may be greather than the natural limit. @@ -130,7 +130,7 @@ begin if C not in '0' .. '9' then Error_Msg_Scan ("a dot must be followed by a digit"); Current_Token := Tok_Real; - Current_Context.Fp64 := Fp64 (To_Float_64 (False, Res, Base, 0)); + Current_Context.Lit_Fp64 := Fp64 (To_Float_64 (False, Res, Base, 0)); return; end if; Scan_Integer; @@ -283,7 +283,7 @@ begin -- a universal real. Current_Token := Tok_Real; - Current_Context.Fp64 := + Current_Context.Lit_Fp64 := Fp64 (To_Float_64 (False, Res, Base, Exp - Scale)); else -- a universal integer. @@ -298,10 +298,10 @@ begin U : Unsigned_64; begin Bignum_To_Int (Res, U, Ok); - if U > Unsigned_64 (Iir_Int64'Last) then + if U > Unsigned_64 (Int64'Last) then Ok := False; else - Current_Context.Int64 := Iir_Int64 (U); + Current_Context.Lit_Int64 := Int64 (U); end if; end; if not Ok then @@ -313,5 +313,5 @@ exception Error_Msg_Scan ("literal overflow"); Current_Token := Tok_Integer; - Current_Context.Int64 := 0; + Current_Context.Lit_Int64 := 0; end Scan_Literal; diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index 734b0c7ce..5c787d756 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -158,8 +158,8 @@ package body Vhdl.Scanner is Str_Id : String8_Id; Str_Len : Nat32; Identifier: Name_Id; - Int64 : Iir_Int64; - Fp64 : Iir_Fp64; + Lit_Int64 : Int64; + Lit_Fp64 : Fp64; end record; pragma Suppress_Initialization (Scan_Context); @@ -212,8 +212,8 @@ package body Vhdl.Scanner is Bit_Str_Sign => ' ', Str_Id => Null_String8, Str_Len => 0, - Int64 => 0, - Fp64 => 0.0); + Lit_Int64 => 0, + Lit_Fp64 => 0.0); Source: File_Buffer_Acc renames Current_Context.Source; Pos: Source_Ptr renames Current_Context.Pos; @@ -259,14 +259,14 @@ package body Vhdl.Scanner is return Current_Context.Bit_Str_Sign; end Get_Bit_String_Sign; - function Current_Iir_Int64 return Iir_Int64 is + function Current_Iir_Int64 return Int64 is begin - return Current_Context.Int64; + return Current_Context.Lit_Int64; end Current_Iir_Int64; - function Current_Iir_Fp64 return Iir_Fp64 is + function Current_Iir_Fp64 return Fp64 is begin - return Current_Context.Fp64; + return Current_Context.Lit_Fp64; end Current_Iir_Fp64; function Get_Current_Source_File return Source_File_Entry is @@ -333,8 +333,8 @@ package body Vhdl.Scanner is Bit_Str_Sign => ' ', Str_Id => Null_String8, Str_Len => 0, - Int64 => -1, - Fp64 => 0.0); + Lit_Int64 => -1, + Lit_Fp64 => 0.0); Current_Token := Tok_Invalid; end Set_File; diff --git a/src/vhdl/vhdl-scanner.ads b/src/vhdl/vhdl-scanner.ads index 797e2f6e1..64f54bb3b 100644 --- a/src/vhdl/vhdl-scanner.ads +++ b/src/vhdl/vhdl-scanner.ads @@ -59,11 +59,11 @@ package Vhdl.Scanner is -- When CURRENT_TOKEN is tok_integer, returns the value. -- When CURRENT_TOKEN is tok_bit_string, returns the log of the base. - function Current_Iir_Int64 return Iir_Int64; + function Current_Iir_Int64 return Int64; pragma Inline (Current_Iir_Int64); -- When CURRENT_TOKEN is tok_real, it returns the value. - function Current_Iir_Fp64 return Iir_Fp64; + function Current_Iir_Fp64 return Fp64; pragma Inline (Current_Iir_Fp64); -- Advances the lexical analyser. Put a new token into current_token. diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index 988ee5df4..8f8333cec 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -2068,7 +2068,7 @@ package body Vhdl.Sem_Expr is -- The type of the context is constrained. Index_Type := Get_Index_Type (Lit_Type, 0); if Get_Type_Staticness (Index_Type) = Locally then - if Eval_Discrete_Type_Length (Index_Type) /= Iir_Int64 (Len) then + if Eval_Discrete_Type_Length (Index_Type) /= Int64 (Len) then Error_Msg_Sem (+Lit, "string length does not match that of %n", +Index_Type); end if; @@ -2081,7 +2081,7 @@ package body Vhdl.Sem_Expr is -- Context type is not constained. Set type of the string literal, -- according to LRM93 7.3.2.2. N_Type := Create_Unidim_Array_By_Length - (Lit_Base_Type, Iir_Int64 (Len), Lit); + (Lit_Base_Type, Int64 (Len), Lit); Set_Type (Lit, N_Type); Set_Literal_Subtype (Lit, N_Type); end if; @@ -2206,10 +2206,10 @@ package body Vhdl.Sem_Expr is -- Type of the element of SEL. Sel_El_Type : Iir; -- Number of literals in the element type. - Sel_El_Length : Iir_Int64; + Sel_El_Length : Int64; -- Length of SEL (number of characters in SEL). - Sel_Length : Iir_Int64; + Sel_Length : Int64; -- True if length of a choice mismatches Has_Length_Error : Boolean := False; @@ -2221,7 +2221,7 @@ package body Vhdl.Sem_Expr is procedure Sem_Simple_Choice (Choice : Iir) is Expr : Iir; - Choice_Len : Iir_Int64; + Choice_Len : Int64; begin -- LRM93 8.8 -- In such case, each choice appearing in any of the case statement @@ -2364,7 +2364,7 @@ package body Vhdl.Sem_Expr is -- easily overflow. if Info.Others_Choice = Null_Iir then declare - Nbr : Iir_Int64 := Iir_Int64 (Info.Nbr_Choices); + Nbr : Int64 := Int64 (Info.Nbr_Choices); begin for I in 1 .. Sel_Length loop Nbr := Nbr / Sel_El_Length; @@ -2537,7 +2537,7 @@ package body Vhdl.Sem_Expr is -- Emit an error message for absence of choices in position L to H -- of index type BT at location LOC. procedure Error_No_Choice (Bt : Iir; - L, H : Iir_Int64; + L, H : Int64; Loc : Location_Type) is begin if L = H then @@ -2551,9 +2551,9 @@ package body Vhdl.Sem_Expr is -- Lowest and highest bounds. Lb, Hb : Iir; - Pos : Iir_Int64; - Pos_Max : Iir_Int64; - E_Pos : Iir_Int64; + Pos : Int64; + Pos_Max : Int64; + E_Pos : Int64; Choice : Iir; Need_Others : Boolean; @@ -2654,7 +2654,7 @@ package body Vhdl.Sem_Expr is Is_Case_Stmt : Boolean) is -- Number of positionnal choice. - Nbr_Pos : Iir_Int64; + Nbr_Pos : Int64; -- Number of named choices. Nbr_Named : Natural; @@ -2664,7 +2664,7 @@ package body Vhdl.Sem_Expr is Has_Error : Boolean; - Pos_Max : Iir_Int64; + Pos_Max : Int64; El : Iir; Prev_El : Iir; @@ -3593,7 +3593,7 @@ package body Vhdl.Sem_Expr is and then Len_Staticness = Locally then Info.Index_Subtype := Create_Range_Subtype_By_Length - (Index_Type, Iir_Int64 (Len), Get_Location (Aggr)); + (Index_Type, Int64 (Len), Get_Location (Aggr)); end if; else -- Create an index subtype. @@ -3698,7 +3698,7 @@ package body Vhdl.Sem_Expr is Error_Msg_Sem (+Aggr, "subaggregate bounds mismatch"); else if Eval_Discrete_Type_Length (Info.Index_Subtype) - /= Iir_Int64 (Len) + /= Int64 (Len) then Error_Msg_Sem (+Aggr, "subaggregate length mismatch"); end if; @@ -3795,7 +3795,7 @@ package body Vhdl.Sem_Expr is -- Compute ratio of elements vs size of the aggregate to determine -- if the aggregate can be expanded. declare - Size : Iir_Int64; + Size : Int64; begin Size := 1; for I in Infos'Range loop diff --git a/src/vhdl/vhdl-sem_inst.adb b/src/vhdl/vhdl-sem_inst.adb index 2fa563987..0611fc8f1 100644 --- a/src/vhdl/vhdl-sem_inst.adb +++ b/src/vhdl/vhdl-sem_inst.adb @@ -352,8 +352,8 @@ package body Vhdl.Sem_Inst is Set_Iir_Mode (Res, F, Get_Iir_Mode (N, F)); when Type_Iir_Index32 => Set_Iir_Index32 (Res, F, Get_Iir_Index32 (N, F)); - when Type_Iir_Int64 => - Set_Iir_Int64 (Res, F, Get_Iir_Int64 (N, F)); + when Type_Int64 => + Set_Int64 (Res, F, Get_Int64 (N, F)); when Type_Boolean => Set_Boolean (Res, F, Get_Boolean (N, F)); when Type_Iir_Staticness => @@ -377,8 +377,8 @@ package body Vhdl.Sem_Inst is Set_Iir_Int32 (Res, F, Get_Iir_Int32 (N, F)); when Type_Int32 => Set_Int32 (Res, F, Get_Int32 (N, F)); - when Type_Iir_Fp64 => - Set_Iir_Fp64 (Res, F, Get_Iir_Fp64 (N, F)); + when Type_Fp64 => + Set_Fp64 (Res, F, Get_Fp64 (N, F)); when Type_Token_Type => Set_Token_Type (Res, F, Get_Token_Type (N, F)); when Type_Name_Id => diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 1e104fbff..ac3ec321a 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -1031,7 +1031,7 @@ package body Vhdl.Sem_Names is end if; declare - Dim : Iir_Int64; + Dim : Int64; Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Prefix_Type); begin @@ -1042,7 +1042,7 @@ package body Vhdl.Sem_Names is else Dim := Get_Value (Parameter); end if; - if Dim < 1 or else Dim > Iir_Int64 (Get_Nbr_Elements (Indexes_List)) + if Dim < 1 or else Dim > Int64 (Get_Nbr_Elements (Indexes_List)) then Error_Msg_Sem (+Attr, "parameter value out of bound"); Dim := 1; @@ -3633,7 +3633,7 @@ package body Vhdl.Sem_Names is Set_Simple_Name_Identifier (Res, Id); Attr_Type := Create_Unidim_Array_By_Length (String_Type_Definition, - Iir_Int64 (Name_Table.Get_Name_Length (Id)), + Int64 (Name_Table.Get_Name_Length (Id)), Attr); Set_Simple_Name_Subtype (Res, Attr_Type); Set_Expr_Staticness (Res, Locally); diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 8248aee36..0d30dda9a 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -477,7 +477,7 @@ package body Vhdl.Sem_Stmts is is Expr: Iir; We: Iir_Waveform_Element; - Time, Last_Time : Iir_Int64; + Time, Last_Time : Int64; begin if Get_Kind (Waveform_Chain) = Iir_Kind_Unaffected_Waveform then -- Unaffected. diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 1ecf718f7..aa243bb23 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -318,7 +318,7 @@ package body Vhdl.Sem_Types is return Res; end Range_Expr_To_Type_Definition; - function Create_Physical_Literal (Val : Iir_Int64; Unit : Iir) return Iir + function Create_Physical_Literal (Val : Int64; Unit : Iir) return Iir is Lit : Iir; begin diff --git a/src/vhdl/vhdl-std_package.adb b/src/vhdl/vhdl-std_package.adb index d112b0daf..cb6e3809d 100644 --- a/src/vhdl/vhdl-std_package.adb +++ b/src/vhdl/vhdl-std_package.adb @@ -26,7 +26,7 @@ with Vhdl.Sem_Utils; with Vhdl.Nodes_Utils; use Vhdl.Nodes_Utils; package body Vhdl.Std_Package is - type Bound_Array is array (Boolean) of Iir_Int64; + type Bound_Array is array (Boolean) of Int64; Low_Bound : constant Bound_Array := (False => -(2 ** 31), True => -(2 ** 63)); High_Bound : constant Bound_Array := (False => (2 ** 31) - 1, @@ -120,7 +120,7 @@ package body Vhdl.Std_Package is Set_Visible_Flag (Decl, True); end Set_Std_Identifier; - function Create_Std_Integer (Val : Iir_Int64; Lit_Type : Iir) + function Create_Std_Integer (Val : Int64; Lit_Type : Iir) return Iir_Integer_Literal is Res : Iir_Integer_Literal; @@ -132,7 +132,7 @@ package body Vhdl.Std_Package is return Res; end Create_Std_Integer; - function Create_Std_Fp (Val : Iir_Fp64; Lit_Type : Iir) + function Create_Std_Fp (Val : Fp64; Lit_Type : Iir) return Iir_Floating_Point_Literal is Res : Iir_Floating_Point_Literal; @@ -650,8 +650,8 @@ package body Vhdl.Std_Package is Set_Base_Type (Universal_Real_Subtype_Definition, Universal_Real_Type_Definition); Constraint := Create_Std_Range_Expr - (Create_Std_Fp (Iir_Fp64'First, Universal_Real_Type_Definition), - Create_Std_Fp (Iir_Fp64'Last, Universal_Real_Type_Definition), + (Create_Std_Fp (Fp64'First, Universal_Real_Type_Definition), + Create_Std_Fp (Fp64'Last, Universal_Real_Type_Definition), Universal_Real_Type_Definition); Set_Range_Constraint (Universal_Real_Subtype_Definition, Constraint); Set_Type_Staticness (Universal_Real_Subtype_Definition, Locally); @@ -764,8 +764,8 @@ package body Vhdl.Std_Package is Create_Std_Iir (Iir_Kind_Floating_Subtype_Definition); Set_Base_Type (Real_Subtype_Definition, Real_Type_Definition); Constraint := Create_Std_Range_Expr - (Create_Std_Fp (Iir_Fp64'First, Universal_Real_Type_Definition), - Create_Std_Fp (Iir_Fp64'Last, Universal_Real_Type_Definition), + (Create_Std_Fp (Fp64'First, Universal_Real_Type_Definition), + Create_Std_Fp (Fp64'Last, Universal_Real_Type_Definition), Universal_Real_Type_Definition); Set_Range_Constraint (Real_Subtype_Definition, Constraint); Set_Type_Staticness (Real_Subtype_Definition, Locally); @@ -792,7 +792,7 @@ package body Vhdl.Std_Package is Time_Staticness : Iir_Staticness; First_Unit, Last_Unit : Iir_Unit_Declaration; - function Create_Std_Phys_Lit_Wo_Unit (Value : Iir_Int64; Unit : Iir) + function Create_Std_Phys_Lit_Wo_Unit (Value : Int64; Unit : Iir) return Iir_Physical_Int_Literal is Lit: Iir_Physical_Int_Literal; @@ -806,7 +806,7 @@ package body Vhdl.Std_Package is return Lit; end Create_Std_Phys_Lit_Wo_Unit; - function Create_Std_Phys_Lit (Value : Iir_Int64; Unit : Iir) + function Create_Std_Phys_Lit (Value : Int64; Unit : Iir) return Iir_Physical_Int_Literal is Lit: Iir_Physical_Int_Literal; @@ -820,7 +820,7 @@ package body Vhdl.Std_Package is end Create_Std_Phys_Lit; procedure Create_Unit (Unit : out Iir_Unit_Declaration; - Multiplier_Value : Iir_Int64; + Multiplier_Value : Int64; Multiplier : in Iir_Unit_Declaration; Name : Name_Id) is diff --git a/src/vhdl/vhdl-types.ads b/src/vhdl/vhdl-types.ads index 18b9b2ccb..b9fd673b5 100644 --- a/src/vhdl/vhdl-types.ads +++ b/src/vhdl/vhdl-types.ads @@ -15,6 +15,7 @@ -- along with GHDL; see the file COPYING. If not, write to the Free -- Software Foundation, 59 Temple Place - Suite 330, Boston, MA -- 02111-1307, USA. + with Vhdl.Nodes_Priv; package Vhdl.Types is |