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authorTristan Gingold <tgingold@free.fr>2019-03-25 20:11:06 +0100
committerTristan Gingold <tgingold@free.fr>2019-03-25 20:11:06 +0100
commit0c27469dc815ba0ff3aa8fee61c31b3bba53d695 (patch)
tree1de94b4f496d7b86e1bb8e74fa039aefb5b40c09
parentcd4bb8b71f2eb0b2f6a99dfe44d3daa12c408d89 (diff)
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Add testcase for #787
-rw-r--r--testsuite/gna/issue787/ent.vhdl15
-rwxr-xr-xtestsuite/gna/issue787/testsuite.sh10
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/gna/issue787/ent.vhdl b/testsuite/gna/issue787/ent.vhdl
new file mode 100644
index 000000000..db7063d18
--- /dev/null
+++ b/testsuite/gna/issue787/ent.vhdl
@@ -0,0 +1,15 @@
+entity ent is
+end ent;
+
+architecture a of ent is
+ signal sig_x : bit;
+ signal sig_y : bit;
+
+ signal sig_z : bit_vector(1 downto 0);
+begin
+ -- works
+ -- (sig_x, sig_y) <= sig_z;
+
+ -- "raised TYPES.INTERNAL_ERROR : trans.adb:619"
+ (sig_x, sig_y) <= not sig_z;
+end a;
diff --git a/testsuite/gna/issue787/testsuite.sh b/testsuite/gna/issue787/testsuite.sh
new file mode 100755
index 000000000..9bc0d1b47
--- /dev/null
+++ b/testsuite/gna/issue787/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze ent.vhdl
+elab_simulate ent
+
+clean
+
+echo "Test successful"