iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	testsuite/gna: add a test for #2147	Tristan Gingold	2022-07-28	3	-0/+41
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*	vhdl-sem_names: add implicit function call for array attributes. Fix #2147	Tristan Gingold	2022-07-28	1	-40/+8
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*	options.adb: -Werror=X enables warning X.	Tristan Gingold	2022-07-28	1	-0/+1
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*	testsuite/synth: adjust test for #2144	Tristan Gingold	2022-07-28	2	-3/+1
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*	synth-vhdl_expr: add support for branch quantities	Tristan Gingold	2022-07-28	2	-0/+2
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*	simul-vhdl_simul: add scalar terminal table	Tristan Gingold	2022-07-28	1	-0/+16
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*	simul-vhdl_debug: add info terminal	Tristan Gingold	2022-07-28	1	-20/+69
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*	testsuite/gna: add a test for #2141	Tristan Gingold	2022-07-28	4	-0/+119
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*	vhdl-sem_names: allow element attribute on element attribute. Fix #2141	Tristan Gingold	2022-07-28	4	-17/+34
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*	testsuite/synth: add a test for #2144	Tristan Gingold	2022-07-27	4	-0/+120
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*	elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144	Tristan Gingold	2022-07-27	1	-9/+17
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*	ci: macos-10.15 is deprecated, use macos-11 and macos-12	Unai Martinez-Corral	2022-07-27	1	-2/+2
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*	testsuite/synth: add a test for #2139	Tristan Gingold	2022-07-27	2	-0/+26
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*	synth-disp_vhdl: improve output for unsigned. Fix #2139	Tristan Gingold	2022-07-27	1	-2/+17
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*	testsuite/synth: add tests for #2143	Tristan Gingold	2022-07-27	5	-0/+102
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*	elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elab	Tristan Gingold	2022-07-27	1	-0/+9
\| \| \| \|	Fix #2143
*	synthesis.adb: cleanup after expand. For #2142	Tristan Gingold	2022-07-27	1	-0/+2
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*	netlists-disp_vhdl: adjust output for #2140	Tristan Gingold	2022-07-27	1	-2/+8
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*	testsuite/synth: add a test for #2142	Tristan Gingold	2022-07-27	2	-0/+33
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*	netlists-expands: do not try to clean input of dyn_extract. Fix #2142	Tristan Gingold	2022-07-27	1	-5/+1
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*	testsuite/synth: add a test for #2140	Tristan Gingold	2022-07-26	2	-0/+77
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*	netlist-disp_vhdl: add a separator between instances and signals.	Tristan Gingold	2022-07-26	1	-1/+1
\| \| \| \|	Fix #2140
*	vhdl-parse: set reference_terminal flag	Tristan Gingold	2022-07-26	1	-0/+1
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*	testsuite/gna: add a test for #2138	Tristan Gingold	2022-07-25	2	-0/+40
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*	vhdl-canon: handle conditional variable assignment. Fix #2138	Tristan Gingold	2022-07-25	1	-1/+16
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*	simul: gather terminals	Tristan Gingold	2022-07-25	4	-3/+74
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*	synth/elab-vhdl_values: add Value_Terminal	Tristan Gingold	2022-07-25	6	-4/+38
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*	vhdl-nodes: add Get/Set_Reference_Terminal_Flag	Tristan Gingold	2022-07-25	6	-478/+541
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*	synth-environment: fix memory crash. Fix #2139	Tristan Gingold	2022-07-25	1	-2/+8
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*	dyn_tables,tables: add Reserve. For #2139	Tristan Gingold	2022-07-25	4	-5/+28
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*	src/simul: rewrite of ghdl/simul based on synth	Tristan Gingold	2022-07-24	7	-0/+3759
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*	synth: add hook for dot attribute	Tristan Gingold	2022-07-24	3	-7/+17
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*	pyGHDL/lsp: fix after renaming	Tristan Gingold	2022-07-22	1	-1/+1
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*	testsuite/gna: add a test for #2136	Tristan Gingold	2022-07-21	3	-0/+70
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*	vhdl: handle element attribute in declarations. Fix #2136	Tristan Gingold	2022-07-21	2	-12/+23
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*	elab-vhdl_decls: elaborate dot attribute	Tristan Gingold	2022-07-21	3	-4/+14
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*	vhdl-nodes: renaming.	Tristan Gingold	2022-07-21	23	-143/+145
\| \| \| \| \| \| \|	Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
*	elab-vhdl_decls: elaborate implicit signals	Tristan Gingold	2022-07-21	1	-2/+23
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*	Makefile.in: allow build of ghdl_mcode with sundials enabled	Tristan Gingold	2022-07-21	2	-1/+26
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*	synth-vhdl_expr: add hook for quantities	Tristan Gingold	2022-07-20	2	-11/+23
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*	elab-vhdl_debug: handle signals in packages	Tristan Gingold	2022-07-20	1	-2/+8
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*	grt: add analog_solver (work in progress)	Tristan Gingold	2022-07-20	4	-9/+197
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*	grt: add real now variable.	Tristan Gingold	2022-07-20	4	-0/+19
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*	ghdlsimul: simplify elaboration circuitery	Tristan Gingold	2022-07-20	1	-13/+0
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*	elab-vhdl_context: add iterator for top-level packages	Tristan Gingold	2022-07-20	2	-0/+36
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*	configure: add --with-sundials (preliminary work)	Tristan Gingold	2022-07-20	4	-1/+56
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*	elab-vhdl_debug: disp fp64 values	Tristan Gingold	2022-07-20	4	-2/+10
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*	testsuite/gna: add a test for #2134	Tristan Gingold	2022-07-16	3	-0/+61
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*	vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134	Tristan Gingold	2022-07-16	1	-0/+2
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*	vhdl: preliminary work to elaborat quantities	Tristan Gingold	2022-07-16	7	-2/+26
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