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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-21 21:33:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-21 21:34:44 +0200 |
| commit | 162561a5659c6276368fde2fd5eaebd8400c0e57 (patch) | |
| tree | 038807d726395a01a6bd7f17bbaf795be3f66c0c | |
| parent | 341a8698ccb6b795d46b9570bac06e240c7664de (diff) | |
| download | ghdl-162561a5659c6276368fde2fd5eaebd8400c0e57.tar.gz ghdl-162561a5659c6276368fde2fd5eaebd8400c0e57.tar.bz2 ghdl-162561a5659c6276368fde2fd5eaebd8400c0e57.zip | |
elab-vhdl_decls: elaborate dot attribute
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 13 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_decls.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_names.adb | 2 |
3 files changed, 14 insertions, 4 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index ffa0ee0a7..afeb344aa 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -180,6 +180,17 @@ package body Elab.Vhdl_Decls is Create_Signal (Syn_Inst, Decl, Obj_Typ, null); end Elab_Implicit_Signal_Declaration; + procedure Elab_Implicit_Quantity_Declaration (Syn_Inst : Synth_Instance_Acc; + Decl : Node) + is + Obj_Typ : Type_Acc; + Res : Valtyp; + begin + Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); + Res := Create_Value_Quantity (Obj_Typ, No_Quantity_Index); + Create_Object (Syn_Inst, Decl, Res); + end Elab_Implicit_Quantity_Declaration; + procedure Elab_Attribute_Specification (Syn_Inst : Synth_Instance_Acc; Spec : Node) is @@ -316,6 +327,8 @@ package body Elab.Vhdl_Decls is Elab_Free_Quantity_Declaration (Syn_Inst, Decl); when Iir_Kind_Above_Attribute => Elab_Implicit_Signal_Declaration (Syn_Inst, Decl); + when Iir_Kind_Dot_Attribute => + Elab_Implicit_Quantity_Declaration (Syn_Inst, Decl); when Iir_Kinds_Signal_Attribute => -- Not supported by synthesis. null; diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 11a07a1ae..8d7cbe50f 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -68,9 +68,6 @@ package body Vhdl.Sem_Decls is is Decl : Iir; begin - -- We deal only with signal attribute. - pragma Assert (Get_Kind (Attr) in Iir_Kinds_AMS_Signal_Attribute); - -- There must be a declarative part for implicit signals. pragma Assert (Current_Signals_Region.Decls_Parent /= Null_Iir); diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index e7a1f836a..3993cae22 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -2030,7 +2030,7 @@ package body Vhdl.Sem_Names is return Res; when Iir_Kind_Dot_Attribute | Iir_Kind_Integ_Attribute => - -- Already finished. + Sem_Decls.Add_Implicit_Declaration (Res); return Res; when Iir_Kinds_Type_Attribute | Iir_Kind_Subtype_Attribute |