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*
testsuite/synth: add a test for #2149
Tristan Gingold
2022-07-28
2
-0
/
+70
|
*
netlists-disp_verilog(disp_const_log): fix output. Fix #2149
Tristan Gingold
2022-07-28
1
-2
/
+2
|
*
testsuite/synth: add a test for #2145
Tristan Gingold
2022-07-28
2
-0
/
+48
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*
synth-disp_vhdl: fix out conversion. Fix #2145
Tristan Gingold
2022-07-28
1
-21
/
+29
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In the case the width of a vector is only 1 bit
*
testsuite/gna: add tests for #2148
Tristan Gingold
2022-07-28
5
-0
/
+90
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*
vhdl: check read for attribute parameter and aggregates. Fix #2148
Tristan Gingold
2022-07-28
2
-3
/
+20
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*
testsuite/gna: add a test for #2147
Tristan Gingold
2022-07-28
3
-0
/
+41
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*
vhdl-sem_names: add implicit function call for array attributes. Fix #2147
Tristan Gingold
2022-07-28
1
-40
/
+8
|
*
options.adb: -Werror=X enables warning X.
Tristan Gingold
2022-07-28
1
-0
/
+1
|
*
testsuite/synth: adjust test for #2144
Tristan Gingold
2022-07-28
2
-3
/
+1
|
*
synth-vhdl_expr: add support for branch quantities
Tristan Gingold
2022-07-28
2
-0
/
+2
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*
simul-vhdl_simul: add scalar terminal table
Tristan Gingold
2022-07-28
1
-0
/
+16
|
*
simul-vhdl_debug: add info terminal
Tristan Gingold
2022-07-28
1
-20
/
+69
|
*
testsuite/gna: add a test for #2141
Tristan Gingold
2022-07-28
4
-0
/
+119
|
*
vhdl-sem_names: allow element attribute on element attribute. Fix #2141
Tristan Gingold
2022-07-28
4
-17
/
+34
|
*
testsuite/synth: add a test for #2144
Tristan Gingold
2022-07-27
4
-0
/
+120
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*
elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144
Tristan Gingold
2022-07-27
1
-9
/
+17
|
*
ci: macos-10.15 is deprecated, use macos-11 and macos-12
Unai Martinez-Corral
2022-07-27
1
-2
/
+2
|
*
testsuite/synth: add a test for #2139
Tristan Gingold
2022-07-27
2
-0
/
+26
|
*
synth-disp_vhdl: improve output for unsigned. Fix #2139
Tristan Gingold
2022-07-27
1
-2
/
+17
|
*
testsuite/synth: add tests for #2143
Tristan Gingold
2022-07-27
5
-0
/
+102
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*
elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elab
Tristan Gingold
2022-07-27
1
-0
/
+9
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Fix #2143
*
synthesis.adb: cleanup after expand. For #2142
Tristan Gingold
2022-07-27
1
-0
/
+2
|
*
netlists-disp_vhdl: adjust output for #2140
Tristan Gingold
2022-07-27
1
-2
/
+8
|
*
testsuite/synth: add a test for #2142
Tristan Gingold
2022-07-27
2
-0
/
+33
|
*
netlists-expands: do not try to clean input of dyn_extract. Fix #2142
Tristan Gingold
2022-07-27
1
-5
/
+1
|
*
testsuite/synth: add a test for #2140
Tristan Gingold
2022-07-26
2
-0
/
+77
|
*
netlist-disp_vhdl: add a separator between instances and signals.
Tristan Gingold
2022-07-26
1
-1
/
+1
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Fix #2140
*
vhdl-parse: set reference_terminal flag
Tristan Gingold
2022-07-26
1
-0
/
+1
|
*
testsuite/gna: add a test for #2138
Tristan Gingold
2022-07-25
2
-0
/
+40
|
*
vhdl-canon: handle conditional variable assignment. Fix #2138
Tristan Gingold
2022-07-25
1
-1
/
+16
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*
simul: gather terminals
Tristan Gingold
2022-07-25
4
-3
/
+74
|
*
synth/elab-vhdl_values: add Value_Terminal
Tristan Gingold
2022-07-25
6
-4
/
+38
|
*
vhdl-nodes: add Get/Set_Reference_Terminal_Flag
Tristan Gingold
2022-07-25
6
-478
/
+541
|
*
synth-environment: fix memory crash. Fix #2139
Tristan Gingold
2022-07-25
1
-2
/
+8
|
*
dyn_tables,tables: add Reserve. For #2139
Tristan Gingold
2022-07-25
4
-5
/
+28
|
*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
7
-0
/
+3759
|
*
synth: add hook for dot attribute
Tristan Gingold
2022-07-24
3
-7
/
+17
|
*
pyGHDL/lsp: fix after renaming
Tristan Gingold
2022-07-22
1
-1
/
+1
|
*
testsuite/gna: add a test for #2136
Tristan Gingold
2022-07-21
3
-0
/
+70
|
*
vhdl: handle element attribute in declarations. Fix #2136
Tristan Gingold
2022-07-21
2
-12
/
+23
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*
elab-vhdl_decls: elaborate dot attribute
Tristan Gingold
2022-07-21
3
-4
/
+14
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*
vhdl-nodes: renaming.
Tristan Gingold
2022-07-21
23
-143
/
+145
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Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
*
elab-vhdl_decls: elaborate implicit signals
Tristan Gingold
2022-07-21
1
-2
/
+23
|
*
Makefile.in: allow build of ghdl_mcode with sundials enabled
Tristan Gingold
2022-07-21
2
-1
/
+26
|
*
synth-vhdl_expr: add hook for quantities
Tristan Gingold
2022-07-20
2
-11
/
+23
|
*
elab-vhdl_debug: handle signals in packages
Tristan Gingold
2022-07-20
1
-2
/
+8
|
*
grt: add analog_solver (work in progress)
Tristan Gingold
2022-07-20
4
-9
/
+197
|
*
grt: add real now variable.
Tristan Gingold
2022-07-20
4
-0
/
+19
|
*
ghdlsimul: simplify elaboration circuitery
Tristan Gingold
2022-07-20
1
-13
/
+0
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