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* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
* | vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
* | vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
* | synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
* | vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-304-196/+241
* | std_names: add std_matchTristan Gingold2019-08-302-3/+5
* | vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-305-114/+137
* | synth: handle enumeration subtype in ranges.Tristan Gingold2019-08-301-1/+2
* | synth: fix named association in record aggregate.Tristan Gingold2019-08-301-1/+3
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* testsuite/synth: add testcase for records. Temporary disable stmt01Tristan Gingold2019-08-295-0/+168
* synth: add support for record types.Tristan Gingold2019-08-2913-82/+361
* synth: Integer operators (#902)marph912019-08-283-0/+47
* testsuite/synth: testcase for conditional signal assignment.Tristan Gingold2019-08-273-0/+61
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-272-0/+3
* testsuite/synth: add cases for assign.Tristan Gingold2019-08-274-4/+62
* testsuite/synth: add asgn01Tristan Gingold2019-08-275-0/+124
* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* Makefile.in: Add .NOTPARALLEL. For #888Tristan Gingold2019-08-271-0/+9
* testsuite/synth: add fsm02 test.Tristan Gingold2019-08-275-0/+181
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-207-6/+77
* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
* testsuite/synth: add a test for previous commit.Tristan Gingold2019-08-202-0/+13
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-203-13/+53
* vhdl-prints: handle verification units.Tristan Gingold2019-08-201-318/+354
* testsuite/synth: add a test for assume directive in verification units.Tristan Gingold2019-08-202-2/+11
* vhdl: handle assume in verification units.Tristan Gingold2019-08-205-1/+11
* testsuite/synth: add psl02Tristan Gingold2019-08-204-0/+74
* synth: analyze input files.Tristan Gingold2019-08-201-1/+8
* synth: set location on assume/assert gates.Tristan Gingold2019-08-203-8/+19
* synth: handle verification units.Tristan Gingold2019-08-2015-491/+703
* synth: handle array attribute "length" (#895)marph912019-08-191-0/+10
* synth: add testcase for issue 34Tristan Gingold2019-08-1713-0/+442
* synth: fix tgingold/ghdlsynth#34 (association).Tristan Gingold2019-08-171-2/+1
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-1716-605/+792
* testsuite/synth: add reproducer for tgingold/ghdlsynth-beta#33Tristan Gingold2019-08-163-0/+73
* synth: handle integer values in subtype conversion.Tristan Gingold2019-08-161-0/+2
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-1615-759/+1061
* testsuite: strenghten a testcase.Tristan Gingold2019-08-161-0/+1
* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-169-737/+774
* testsuite/python: fix test name (to follow the testsuite.sh convention)Tristan Gingold2019-08-163-0/+0
* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
* Makefile.in: install synth include files as part of libghdl.Tristan Gingold2019-08-151-1/+6
* configure: complete --helpTristan Gingold2019-08-151-0/+2