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author | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:46:26 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:46:26 +0200 |
commit | b77eb1a27fa6838c7194a44f8d872005d08e6ac7 (patch) | |
tree | 82433c97f5271cae91191301b72e5bfbf63b8067 | |
parent | d81dfb85709da4daa9bac3fceec5716a0b410b5b (diff) | |
download | ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.tar.gz ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.tar.bz2 ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.zip |
testsuite/synth: add psl02
-rw-r--r-- | testsuite/synth/psl02/assert1.vhdl | 30 | ||||
-rw-r--r-- | testsuite/synth/psl02/assert2.vhdl | 24 | ||||
-rwxr-xr-x | testsuite/synth/psl02/testsuite.sh | 15 | ||||
-rw-r--r-- | testsuite/synth/psl02/verif1.vhdl | 5 |
4 files changed, 74 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/assert1.vhdl b/testsuite/synth/psl02/assert1.vhdl new file mode 100644 index 000000000..a563dadd1 --- /dev/null +++ b/testsuite/synth/psl02/assert1.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity assert1 is + port (clk, rst: std_logic; + cnt : out unsigned(3 downto 0)); +end assert1; + +architecture behav of assert1 is + signal val : unsigned (3 downto 0); +begin + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + val <= (others => '0'); + else + val <= val + 1; + end if; + end if; + end process; + cnt <= val; +end behav; + +vunit verif1 (assert1) +{ + default clock is rising_edge(clk); + assert always cnt /= 5 abort rst; +} diff --git a/testsuite/synth/psl02/assert2.vhdl b/testsuite/synth/psl02/assert2.vhdl new file mode 100644 index 000000000..0286470c8 --- /dev/null +++ b/testsuite/synth/psl02/assert2.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity assert2 is + port (clk, rst: std_logic; + cnt : out unsigned(3 downto 0)); +end assert2; + +architecture behav of assert2 is + signal val : unsigned (3 downto 0); +begin + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + val <= (others => '0'); + else + val <= val + 1; + end if; + end if; + end process; + cnt <= val; +end behav; diff --git a/testsuite/synth/psl02/testsuite.sh b/testsuite/synth/psl02/testsuite.sh new file mode 100755 index 000000000..0e5929ed9 --- /dev/null +++ b/testsuite/synth/psl02/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth assert1.vhdl -e assert1 > syn_assert1.vhdl +analyze syn_assert1.vhdl + +synth assert2.vhdl verif1.vhdl -e assert2 > syn_assert2.vhdl +analyze syn_assert2.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/synth/psl02/verif1.vhdl b/testsuite/synth/psl02/verif1.vhdl new file mode 100644 index 000000000..5aeb9559f --- /dev/null +++ b/testsuite/synth/psl02/verif1.vhdl @@ -0,0 +1,5 @@ +vunit verif1 (assert2) +{ + default clock is rising_edge(clk); + assert always cnt /= 5 abort rst; +} |