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* synth-vhdl_eval: handle more operations (to_string, match)Tristan Gingold2022-05-312-23/+229
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* doc: update links to Yosys website (#2069)Xiretza2022-05-312-5/+5
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* Merge pull request #2067 from sudden6/fix_configuretgingold2022-05-311-1/+1
|\ | | | | use --version flag to check for C compiler
| * use --version flag to check for C compilersudden62022-05-301-1/+1
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* synth-vhdl_eval: handle more operatorsTristan Gingold2022-05-303-26/+402
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* synth-vhdl_static_proc: add hook for std.env.finishTristan Gingold2022-05-302-0/+12
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* synth-vhdl_oper: add hooks for bit edgeTristan Gingold2022-05-302-0/+15
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* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-304-211/+214
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* elab-vhdl_objtypes: bit and logic types also have a rangeTristan Gingold2022-05-302-6/+13
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-295-23/+219
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* synth-vhdl_eval: handle resolution_limitTristan Gingold2022-05-291-0/+3
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* vhdl: recognize subprograms from std.envTristan Gingold2022-05-295-484/+587
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* std_names: add names from std.envTristan Gingold2022-05-293-374/+387
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* elab-debugger: export more subprogramsTristan Gingold2022-05-291-0/+6
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* ghdlsimul: use assertion level from command lineTristan Gingold2022-05-291-0/+2
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* synth-vhdl_stmts: export two procedures, adjust assertion messageTristan Gingold2022-05-292-5/+10
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* synth-vhdl_oper: add hook for falling edge, handle aliases.Tristan Gingold2022-05-293-3/+13
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-0/+30
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* elab-vhdl_objtypes: add unshare with areapoolTristan Gingold2022-05-292-0/+13
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* synth: handle suspend state declaration and statementTristan Gingold2022-05-272-0/+16
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* ghdlsimul: initial stop is after elaborationTristan Gingold2022-05-271-8/+1
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* elab-debugger: add Debug_TimeTristan Gingold2022-05-272-1/+16
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* elab-vhdl_debug: handle records in disp_memtyp.Tristan Gingold2022-05-272-4/+32
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* elab-vhdl_objtypes: add Create_Memory_U32 (for states)Tristan Gingold2022-05-272-3/+19
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* utils_io: add put_addr (to display addresses)Tristan Gingold2022-05-272-0/+24
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* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-2613-199/+574
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* synth: move procedure call copyback values in contextTristan Gingold2022-05-253-79/+82
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* vhdl-annotations: annotate procedure call associationsTristan Gingold2022-05-251-14/+47
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* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-253-12/+16
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* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-258-72/+203
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* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-2412-56/+52
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* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
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* synth-vhdl_eval: handle element-element concatenationTristan Gingold2022-05-241-0/+18
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* elab-vhdl_values-debug: slightly improve outputTristan Gingold2022-05-241-2/+6
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* testsuite/synth: add a commentsTristan Gingold2022-05-231-0/+2
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* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
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* synth-vhdl_oper: add an hook for rising_edgeTristan Gingold2022-05-233-4/+13
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* elab-vhdl_objtypes: replace Is_Synth by WkindTristan Gingold2022-05-223-23/+40
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* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-229-70/+36
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* synth: also use one-dimensional unbounded arrays for objtypesTristan Gingold2022-05-226-58/+66
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* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-2215-137/+113
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* elab-vhdl_values-debug: improve debug_typ outputTristan Gingold2022-05-221-14/+37
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* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-2217-552/+340
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* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-212-14/+29
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* synth-vhdl_expr: avoid a memocy copyTristan Gingold2022-05-211-3/+7
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* vhdl-canon: remove unused canon_flag_inertial_associationsTristan Gingold2022-05-203-9/+0
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* synth/elab-vhdl_values: use a proper type for signal_indexTristan Gingold2022-05-195-7/+11
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* testsuite/synth: add a test for #2063Tristan Gingold2022-05-182-0/+39
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* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
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* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
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