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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-23 06:45:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-23 06:45:07 +0200 |
| commit | 84516bdbe86290f475ad177371975991d38d065c (patch) | |
| tree | ff5cf21594a363c400c65ff6fda765a655ccada3 | |
| parent | 97653b03a7e13d1e85cb88bd5ffe222ac23cf86f (diff) | |
| download | ghdl-84516bdbe86290f475ad177371975991d38d065c.tar.gz ghdl-84516bdbe86290f475ad177371975991d38d065c.tar.bz2 ghdl-84516bdbe86290f475ad177371975991d38d065c.zip | |
testsuite/synth: add a comments
| -rw-r--r-- | testsuite/synth/arr01/tb_arr04.vhdl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/testsuite/synth/arr01/tb_arr04.vhdl b/testsuite/synth/arr01/tb_arr04.vhdl index 51801b258..63e01fa85 100644 --- a/testsuite/synth/arr01/tb_arr04.vhdl +++ b/testsuite/synth/arr01/tb_arr04.vhdl @@ -21,6 +21,8 @@ begin constant sov : std_logic_vector := b"0101"; constant v_v : std_logic_vector := b"0011"; constant r_v : std_logic_vector := b"0001"; + -- reg0 0001 + -- reg1 0011 begin clk <= '0'; rst <= '1'; |