synth/elab-vhdl_values: use a proper type for signal_index

5 files changed, 11 insertions, 7 deletions

diff --git a/src/synth/elab-vhdl_context.adb b/src/synth/elab-vhdl_context.adb
index 717b90dd2..7211c01f0 100644
--- a/src/synth/elab-vhdl_context.adb
+++ b/src/synth/elab-vhdl_context.adb
@@ -25,7 +25,7 @@ with Vhdl.Utils;
 
 package body Elab.Vhdl_Context is
 
-   Sig_Nbr : Signal_Index_Type := 0;
+   Sig_Nbr : Signal_Index_Type := No_Signal_Index;
 
    function Get_Nbr_Signal return Signal_Index_Type is
    begin
@@ -305,8 +305,8 @@ package body Elab.Vhdl_Context is
       Vt : Valtyp;
    begin
       Create_Object (Syn_Inst, Info.Slot, 1);
-      Vt := (Typ, Create_Value_Signal (Sig_Nbr, Init));
       Sig_Nbr := Sig_Nbr + 1;
+      Vt := (Typ, Create_Value_Signal (Sig_Nbr, Init));
       Syn_Inst.Objects (Info.Slot) := (Kind => Obj_Object, Obj => Vt);
    end Create_Signal;
 
diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb
index 79153d4cd..f7820edf5 100644
--- a/src/synth/elab-vhdl_debug.adb
+++ b/src/synth/elab-vhdl_debug.adb
@@ -190,7 +190,7 @@ package body Elab.Vhdl_Debug is
          when Value_Signal =>
             Put ("signal");
             Put (' ');
-            Put_Uns32 (Vt.Val.S);
+            Put_Uns32 (Uns32 (Vt.Val.S));
          when Value_File =>
             Put ("file");
          when Value_Const =>
diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb
index 193515e27..15da440e1 100644
--- a/src/synth/elab-vhdl_values-debug.adb
+++ b/src/synth/elab-vhdl_values-debug.adb
@@ -165,7 +165,8 @@ package body Elab.Vhdl_Values.Debug is
       case M.Typ.Kind is
          when Type_Bit
            | Type_Logic =>
-            Put ("bit/logic");
+            Put ("bit/logic: ");
+            Put_Uns32 (Uns32 (Read_U8 (M.Mem)));
          when Type_Vector =>
             Put ("vector (");
             Debug_Bound (M.Typ.Vbound, True);
diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb
index 017edc700..59bc63293 100644
--- a/src/synth/elab-vhdl_values.adb
+++ b/src/synth/elab-vhdl_values.adb
@@ -102,7 +102,8 @@ package body Elab.Vhdl_Values is
         (Alloc (Current_Pool, Value_Type_Net'(Kind => Value_Net, N => S)));
    end Create_Value_Net;
 
-   function Create_Value_Signal (S : Uns32; Init : Value_Acc) return Value_Acc
+   function Create_Value_Signal (S : Signal_Index_Type; Init : Value_Acc)
+                                return Value_Acc
    is
       subtype Value_Type_Signal is Value_Type (Value_Signal);
       function Alloc is new Areapools.Alloc_On_Pool_Addr (Value_Type_Signal);
diff --git a/src/synth/elab-vhdl_values.ads b/src/synth/elab-vhdl_values.ads
index 1838fef9c..539edd3eb 100644
--- a/src/synth/elab-vhdl_values.ads
+++ b/src/synth/elab-vhdl_values.ads
@@ -67,7 +67,8 @@ package Elab.Vhdl_Values is
 
    subtype File_Index is Grt.Files_Operations.Ghdl_File_Index;
 
-   subtype Signal_Index_Type is Uns32;
+   type Signal_Index_Type is new Uns32;
+   No_Signal_Index : constant Signal_Index_Type := 0;
 
    type Value_Type (Kind : Value_Kind) is record
       case Kind is
@@ -119,7 +120,8 @@ package Elab.Vhdl_Values is
    --  Create a Value_Wire.
    function Create_Value_Wire (S : Uns32) return Value_Acc;
 
-   function Create_Value_Signal (S : Uns32; Init : Value_Acc) return Value_Acc;
+   function Create_Value_Signal (S : Signal_Index_Type; Init : Value_Acc)
+                                return Value_Acc;
 
    function Create_Value_Memory (Vtype : Type_Acc) return Valtyp;
    function Create_Value_Memory (Mt : Memtyp) return Valtyp;