doc: update links to Yosys website (#2069)

2 files changed, 5 insertions, 5 deletions

diff --git a/README.md b/README.md
index f6fd0862e..5bfa80ada 100644
--- a/README.md
+++ b/README.md
@@ -63,7 +63,7 @@ GHDL is free software:
 
 - The CLI tool allows analysis, compilation, simulation and (experimental) synthesis for generating VHDL 1993 netlists. It is written in Ada and C, and three different backends are supported, which are sometimes named `ghdl_mcode`, `ghdl_gcc` and `ghdl_llvm`. This is the entrypoint for most users.
 
-- **[experimental]** [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) is the integration of GHDL as a frontend plugin module for [Yosys Open SYnthesis Suite](http://www.clifford.at/yosys/), which uses the `libghdl` library (built with `--enable-synth`).
+- **[experimental]** [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) is the integration of GHDL as a frontend plugin module for [Yosys Open SYnthesis Suite](https://yosyshq.net/yosys/), which uses the `libghdl` library (built with `--enable-synth`).
 
 - `ghdl-ls` (part of pyGHDL, see below) implements Language Server Protocol (LSP) in Python. VHDL analysis features provided by GHDL are accessed through `libghdl`. This can be integrated in text editors or IDES, such as, Vim, Emacs, Atom or Visual Studio Code. See [ghdl/ghdl-language-server](https://github.com/ghdl/ghdl-language-server).
   - [vscode-client](https://github.com/ghdl/ghdl-language-server/tree/master/vscode-client) is an extension for [Visual Studio Code (VSC)](https://code.visualstudio.com/) to provide language support for VHDL by interfacing `ghdl-ls`.
diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst
index d3968fe67..953e0ec8b 100644
--- a/doc/using/Synthesis.rst
+++ b/doc/using/Synthesis.rst
@@ -138,7 +138,7 @@ Assertions, PSL and formal verification
 
   Treat all PSL asserts like PSL assumes. If this option is used, GHDL generates an `assume` directive
   for each `assert` directive during synthesis. This is similar to the `-assert-assumes`
-  option of Yosys' `read_verilog <http://www.clifford.at/yosys/cmd_read_verilog.html>`_ command.
+  option of Yosys' `read_verilog <https://yosyshq.net/yosys/cmd_read_verilog.html>`_ command.
 
   Example::
 
@@ -152,7 +152,7 @@ Assertions, PSL and formal verification
 
   Treat all PSL assumes like PSL asserts. If this option is used, GHDL generates an `assert` directive
   for each `assume` directive during synthesis. This is similar to the `-assume-asserts`
-  option of Yosys' `read_verilog <http://www.clifford.at/yosys/cmd_read_verilog.html>`_ command.
+  option of Yosys' `read_verilog <https://yosyshq.net/yosys/cmd_read_verilog.html>`_ command.
 
   Example::
 
@@ -167,7 +167,7 @@ Yosys plugin
 ************
 
 `ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_ is a module to use GHDL as a VHDL front-end for `Yosys
-Open Synthesis Suite <http://www.clifford.at/yosys/>`_, a framework for optimised synthesis and technology mapping.
+Open Synthesis Suite <https://yosyshq.net/yosys/>`_, a framework for optimised synthesis and technology mapping.
 Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification,
 etc. A relevant feature of combining GHDL and Yosys is that mixed-language (VHDL-Verilog) synthesis with open source
 tools is possible.
@@ -190,7 +190,7 @@ Yosys provides ``write_*`` commands for generating output netlists in different
 sources can be converted to EDIF, SMT, BTOR2, etc.
 
 .. HINT:: For a comprehensive list of supported output formats (AIGER, BLIF, ILANG, JSON...), check out the
-  `Yosys documentation <http://www.clifford.at/yosys/documentation.html>`_.
+  `Yosys documentation <https://yosyshq.net/yosys/documentation.html>`_.
 
 To Verilog
 ----------