iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	elab-debugger: remove duplicate flag	Tristan Gingold	2022-06-03	5	-10/+11
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*	areapools: avoid a crash on release with empty block	Tristan Gingold	2022-06-03	1	-0/+1
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*	synth: handle file flush procedure	Tristan Gingold	2022-06-01	3	-0/+18
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*	vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostring	Tristan Gingold	2022-06-01	3	-424/+433
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*	testsuite/gna: add tests for #2070	Tristan Gingold	2022-06-01	63	-0/+272
\| \| \| \|	Close #2070
*	vhdl-utils(is_copyback_parameter): avoid a crash on file parameter	Tristan Gingold	2022-06-01	1	-6/+2
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*	vhdl: improve use of interface types. For #2070	Tristan Gingold	2022-06-01	2	-0/+6
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*	vhdl-scanner: adjust assertion. For #2070	Tristan Gingold	2022-06-01	1	-1/+1
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*	vhdl-parse: do not allow nested context declaration. For #2070	Tristan Gingold	2022-06-01	1	-1/+5
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*	vhdl-parse: avoid a crash on too large numbers. For #2070	Tristan Gingold	2022-06-01	2	-2/+15
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*	vhdl: avoid crash after an error. For #2070	Tristan Gingold	2022-06-01	3	-3/+10
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*	vhdl-evaluation.adb: avoid a crash on overflow. For #2070	Tristan Gingold	2022-06-01	1	-11/+12
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*	vhdl-errors.adb: use normal message subprogram. For #2070	Tristan Gingold	2022-06-01	1	-9/+1
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*	synth-vhdl_eval: complete vector reduce operations	Tristan Gingold	2022-05-31	1	-7/+21
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*	synth-vhdl_eval: handle shift and rotations	Tristan Gingold	2022-05-31	1	-6/+29
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*	synth-vhdl_eval: handle vector match, numeric_bit.to_unsigned	Tristan Gingold	2022-05-31	2	-7/+73
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*	vhdl: recognize numeric_bit.to_unsigned	Tristan Gingold	2022-05-31	5	-225/+283
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*	synth-vhdl_stmts: do not convert out variable on call	Tristan Gingold	2022-05-31	1	-3/+8
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*	synth-vhdl_stmts: export Synth_Subprogram_Back_Association	Tristan Gingold	2022-05-31	2	-7/+15
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*	synth-vhdl_static_proc: handle write_real	Tristan Gingold	2022-05-31	1	-0/+32
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*	synth-vhdl_eval: handle more operations (to_string, match)	Tristan Gingold	2022-05-31	2	-23/+229
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*	doc: update links to Yosys website (#2069)	Xiretza	2022-05-31	2	-5/+5
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*	Merge pull request #2067 from sudden6/fix_configure	tgingold	2022-05-31	1	-1/+1
\|\ \| \| \| \|	use --version flag to check for C compiler
\| *	use --version flag to check for C compiler	sudden6	2022-05-30	1	-1/+1
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*	synth-vhdl_eval: handle more operators	Tristan Gingold	2022-05-30	3	-26/+402
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*	synth-vhdl_static_proc: add hook for std.env.finish	Tristan Gingold	2022-05-30	2	-0/+12
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*	synth-vhdl_oper: add hooks for bit edge	Tristan Gingold	2022-05-30	2	-0/+15
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*	vhdl-nodes: move maximum/minimum out of predefined operator range	Tristan Gingold	2022-05-30	4	-211/+214
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*	elab-vhdl_objtypes: bit and logic types also have a range	Tristan Gingold	2022-05-30	2	-6/+13
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	5	-23/+219
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*	synth-vhdl_eval: handle resolution_limit	Tristan Gingold	2022-05-29	1	-0/+3
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*	vhdl: recognize subprograms from std.env	Tristan Gingold	2022-05-29	5	-484/+587
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*	std_names: add names from std.env	Tristan Gingold	2022-05-29	3	-374/+387
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*	elab-debugger: export more subprograms	Tristan Gingold	2022-05-29	1	-0/+6
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*	ghdlsimul: use assertion level from command line	Tristan Gingold	2022-05-29	1	-0/+2
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*	synth-vhdl_stmts: export two procedures, adjust assertion message	Tristan Gingold	2022-05-29	2	-5/+10
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*	synth-vhdl_oper: add hook for falling edge, handle aliases.	Tristan Gingold	2022-05-29	3	-3/+13
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-0/+30
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*	elab-vhdl_objtypes: add unshare with areapool	Tristan Gingold	2022-05-29	2	-0/+13
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*	synth: handle suspend state declaration and statement	Tristan Gingold	2022-05-27	2	-0/+16
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*	ghdlsimul: initial stop is after elaboration	Tristan Gingold	2022-05-27	1	-8/+1
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*	elab-debugger: add Debug_Time	Tristan Gingold	2022-05-27	2	-1/+16
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*	elab-vhdl_debug: handle records in disp_memtyp.	Tristan Gingold	2022-05-27	2	-4/+32
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*	elab-vhdl_objtypes: add Create_Memory_U32 (for states)	Tristan Gingold	2022-05-27	2	-3/+19
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*	utils_io: add put_addr (to display addresses)	Tristan Gingold	2022-05-27	2	-0/+24
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*	vhdl-canon: add Canon_Add_Suspend_State	Tristan Gingold	2022-05-26	13	-199/+574
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*	synth: move procedure call copyback values in context	Tristan Gingold	2022-05-25	3	-79/+82
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*	vhdl-annotations: annotate procedure call associations	Tristan Gingold	2022-05-25	1	-14/+47
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*	vhdl: move Is_Copyback_Parameter to vhdl-utils	Tristan Gingold	2022-05-25	3	-12/+16
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*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	8	-72/+203
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