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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-31 05:23:08 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-31 18:28:25 +0200 |
| commit | af908ae0045f13ebd067aa4c087ff7f638a14edc (patch) | |
| tree | 6d2ab02203cf764f45c87cc448e63079849a1889 | |
| parent | 83c3d4c32cb724d53128dda7decc66006bad4eef (diff) | |
| download | ghdl-af908ae0045f13ebd067aa4c087ff7f638a14edc.tar.gz ghdl-af908ae0045f13ebd067aa4c087ff7f638a14edc.tar.bz2 ghdl-af908ae0045f13ebd067aa4c087ff7f638a14edc.zip | |
synth-vhdl_stmts: do not convert out variable on call
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 493c412a0..f226e7b59 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -1849,9 +1849,14 @@ package body Synth.Vhdl_Stmts is case Iir_Kinds_Interface_Object_Declaration (Get_Kind (Inter)) is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration => - -- Always passed by value - Val := Synth_Subtype_Conversion - (Ctxt, Val, Inter_Type, True, Assoc); + if Get_Mode (Inter) /= Iir_Out_Mode then + -- Always passed by value + Val := Synth_Subtype_Conversion + (Ctxt, Val, Inter_Type, True, Assoc); + else + -- Use default value ? + null; + end if; when Iir_Kind_Interface_Signal_Declaration => -- LRM08 4.2.2.3 Signal parameters -- If an actual signal is associated with a signal parameter |